EP2AGX95EF29C5G - Arria II GX FPGA, 89K LE, 780-FBGA | Intel
部品番号: EP2AGX95EF29C5G ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $1836.16 | $1,836.16 |
| 10 | $1700 | $17,000.00 |
| 100 | $1550 | $155,000.00 |
| 500 | $1420 | $710,000.00 |
| 1,000 | $1305 | $1,305,000.00 |
EP2AGX95EF29C5G 概要
An FPGA (field-programmable gate array) is a reconfigurable semiconductor device containing an array of programmable logic blocks, interconnect, memory, and increasingly hard IP such as transceivers and DSP blocks. FPGAs sit in the broader taxonomy of programmable logic devices (PLDs) and complement ASICs by offering hardware re-programmability and faster time-to-market. The Arria II GX series specifically targets mid-range transceiver applications, between the low-power Cyclone family and the high-end Stratix family, balancing cost, power, and transceiver performance.
Key features of the EP2AGX95EF29C5G include 372 user I/O pins, dedicated hardware multiplier blocks (DSP blocks) for high-throughput signal processing, embedded memory blocks (M9K) distributed across the fabric, and hard PCI Express (PCIe) Gen1/Gen2 IP cores. The 780-pin FC-FBGA package supports high-speed transceiver signals requiring controlled-impedance escape routing and a low-inductance power distribution network.
Architecturally, the device uses logic elements (LEs) as the basic building block, organized into LABs (logic array blocks), with adaptive logic modules (ALMs) supporting both combinational and registered modes. The transceiver blocks support data rates up to 3.75 Gbps with multiple protocol personalities, including PCIe, SATA, CPRI, and Serial RapidIO.
Typical applications include wireless baseband processing, video broadcasting infrastructure, industrial imaging, radar signal processing, and test and measurement equipment. The device suits any application requiring mid-range logic density combined with high-speed serial I/O.
When designing with this device, careful attention to PCB layout, power integrity, and signal integrity around the transceiver pins is critical. A multi-layer PCB with continuous ground planes and dedicated transceiver power filtering is recommended. Use the Altera Quartus II design tool for synthesis, place-and-route, and timing closure.
This page synthesizes distributor pricing, drop-in FPGA alternatives in the same 780-FBGA footprint, and practical FPGA design considerations not found in the manufacturer datasheet alone.
ドロップイン代替品: EP2AGX95EF29C5G — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EP2AGX95EF29C5G （同一形状・フットプリント） — 相違点: Speed Grade, Package, Transceivers, Operating Temperature, Transceiver Data Rate.
クイック比較ツール — 並列比較する代替部品を選択:
EP2AGX95EF29C4G
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$980 / 個
データシートを見る →EP2AGX95EF29C4N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$855 / 個
データシートを見る →EP2AGX95EF29C3N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$171 / 個
データシートを見る →EP2AGX95EF29C6G
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$465 / 個
データシートを見る →EP2AGX95DF25C6N
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1750 / 個
データシートを見る →EP2AGX125EF29C5G
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$1090 / 個
データシートを見る →EP2AGX95EF29C5G 最大定格＆電気的特性
| Series | Arria II GX |
| Logic Elements | 89,178 |
| LABs/CLBs | 3,747 |
| Total RAM Bits | 6,839,296 |
| User I/O Count | 372 |
| Number of Transceivers | 12 |
| Core Operating Frequency | 500 MHz |
| Process Technology | 40 nm |
| Core Supply Voltage | 0.9 V |
| Package Type | 780-BBGA, FCBGA |
| Package Pin Count | 780 |
| 実装タイプ | Surface Mount |
| 動作温度 | 0C to +85C (Commercial) |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
EP2AGX95EF29C5G ピン構成
| ピン 1 | VCC — Core supply voltage |
| ピン 2 | GND — Ground reference |
| ピン 3 | IO — General purpose user I/O |
| ピン 4 | CLK — Clock input pin |
主な用途
EP2AGX95EF29C5G の用途: 7 件s: Wireless Baseband Processing, Video Broadcasting Infrastructure, Industrial Imaging and Machine Vision, Radar Signal Processing, Test and Measurement Equipment, Medical Imaging Systems, High-Performance Computing Acceleration.
Wireless Baseband Processing
The EP2AGX95EF29C5G's 89,178 logic elements and 12 multi-gigabit transceivers make it well-suited for wireless baseband processing in LTE and WiMAX base stations. The device's M9K memory blocks support chip-rate buffering while DSP blocks handle FFT/iFFT and channel estimation kernels at baseband sample rates. The transceiver channels reach 3.75 Gbps, sufficient for CPRI/OBSAI fronthaul links to remote radio heads. With 372 user I/Os, designers can connect multiple ADC/DAC channels for multi-antenna MIMO configurations without external bus switches.
おすすめ
Video Broadcasting Infrastructure
The EP2AGX95EF29C5G supports broadcast video standards such as SDI, HD-SDI, and 3G-SDI through its transceiver channels, while the abundant logic and DSP resources handle video scaling, deinterlacing, and format conversion. With 6,839,296 bits of embedded memory, the device can buffer multiple video frames simultaneously for PIP or multi-view applications. The 372 user I/O count supports parallel video buses for legacy equipment and provide GPIO for control plane integration. Designers targeting studio-grade equipment benefit from the device's deterministic latency.
おすすめ
Industrial Imaging and Machine Vision
The EP2AGX95EF29C5G provides sufficient logic, memory, and DSP for high-speed line-scan and area-scan camera interfaces including CoaXPress, Camera Link, and GigE Vision. The embedded transceivers support CoaXPress at up to 3.125 Gbps per lane, allowing 4-lane configurations to exceed 10 Gbps aggregate bandwidth. On-chip DSP blocks accelerate image preprocessing, defect detection, and pattern matching algorithms in real time. The 780-pin FCBGA package supports the multi-rail power supply needed for high-speed SERDES while exposing 372 I/Os for parallel sensor and motor control interfaces.
おすすめ
Radar Signal Processing
The EP2AGX95EF29C5G's DSP block count and high-speed transceivers make it suitable for radar front-end preprocessing, including pulse compression, MTI filtering, and CFAR detection. The 12 transceivers handle raw IF data from multiple receive channels while the 89,178 logic elements implement real-time beamforming networks. With 3,747 LABs/CLBs, the device supports the parallel dataflow architectures common in phased-array radar. The commercial 0C-85C temperature range fits indoor and sheltered outdoor installations.
おすすめ
Test and Measurement Equipment
The EP2AGX95EF29C5G integrates high-speed transceivers with abundant logic, making it a strong fit for protocol-aware test equipment such as logic analyzers, BERT testers, and protocol exercisers. The 372 user I/Os provide probe channels with multi-voltage support, while the transceivers handle serial protocol generation and analysis up to 3.75 Gbps. On-chip DSP blocks accelerate real-time eye-diagram measurements and jitter analysis. Designers can use the device's PCIe hard IP to expose the instrument as a PCIe Gen2 endpoint card.
おすすめ
Medical Imaging Systems
The EP2AGX95EF29C5G supports medical imaging modalities including ultrasound, CT, and MRI front-end processing. The DSP blocks accelerate beamforming in ultrasound arrays, while the transceivers handle high-speed analog front-end digitizer links. With 6,839,296 bits of embedded memory, the device buffers raw RF data before image reconstruction. The 780-pin FCBGA provides low-noise power distribution critical for the SNR-limited front-end stages of medical imaging chains.
おすすめ
High-Performance Computing Acceleration
The EP2AGX95EF29C5G can be deployed as a coprocessor in HPC clusters, accelerating workloads such as genomics sequence alignment, financial Monte Carlo simulation, and scientific computing kernels. The PCIe hard IP enables direct host attachment as a Gen2 endpoint, while the DSP blocks accelerate floating-point kernels via custom arithmetic pipelines. With 12 transceivers, the device supports multi-node interconnects such as QPI or proprietary low-latency fabrics in clustered deployments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EP2AGX95EF29C5G — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EP2AGX95EF29C4G | EP2AGX95EF29C4N | EP2AGX95EF29C3N | EP2AGX95EF29C6G |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 780-FBGA (EF29) | 780-FBGA (EF29) | 780-FBGA (EF29) | 780-FBGA (EF29) | 780-FBGA (EF29) |
| Logic Elements | 89,178 | 89,178 | 89,178 | 89,178 | 89,178 |
| Total RAM Bits | 6,839,296 | 6,839,296 | 6,839,296 | 6,839,296 | 6,839,296 |
| User I/O Count | 372 | 372 | 372 | 372 | 372 |
| Number of Transceivers | 12 | 12 | 12 | 12 | 12 |
| Speed Grade | C5 (commercial, mid-speed) | C4 (slower) | C4 (slower) | C3 (slowest) | C6 (fastest) |
| RoHS Compliance | Yes (G suffix) | Yes (G suffix) | No (N suffix) | No (N suffix) | Yes (G suffix) |
| Operating Temperature | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) | 0C to +85C (Commercial) |
主な差別化要因
- Mid-range transceiver density in 780-pin FCBGA （vs EP2AGX95DF25C5G)
- Drop-in speed grade flexibility within EF29 package （vs EP2AGX95EF29C4G)
- RoHS-compliant G-suffix variants （vs EP2AGX95EF29C4N)
設計ノート
The 780-pin flip-chip BGA requires a multi-layer PCB (typically 10-14 layers) with continuous ground planes beneath the device to control impedance for the 12 transceiver channels. Use a 1.0 mm or 1.27 mm pitch BGA footprint with microvia-in-pad or stacked via structures, depending on transceiver data rate. Place transceiver decoupling capacitors within 100 mils of the relevant power balls and use a star-ground isolation strategy between digital and analog supply domains.
The EP2AGX95EF29C5G requires multiple supply rails: 0.9V core, 1.1V auxiliary, 1.5V/1.8V/2.5V/3.3V I/O, and dedicated 1.1V/1.2V PLL/transceiver analog supplies. Estimated total power consumption at full transceiver and DSP utilization is 8-12W. Use a multi-phase PWM regulator for the core rail to meet transient response requirements, and isolate the PLL analog supply with a ferrite bead and bulk capacitor network.
Transceiver channels require matched 100-ohm differential routing with length matching to within 5 mils across P/N pairs and within 50 mils across channels. Maintain 3W spacing from other high-speed signals and avoid crossing power plane splits. Use the Altera Quartus II transceiver tool to set pre-emphasis, equalization, and VOD settings per channel.
Do not confuse the EF29 package (780-pin FCBGA with 12 transceivers) with the DF25 package (572-pin FBGA with fewer transceivers); they are not pin-compatible. Verify the device marking and the Quartus II device library before PCB assembly. Also ensure configuration mode (AS, PS, JTAG) is properly selected and the configuration flash memory is correctly sized for the bitstream.
Estimated: at full load with all 12 transceivers active and 80% logic utilization, total power reaches approximately 10W. With the FCBGA package theta-JA around 12-15 C/W (depending on PCB thermal design), junction temperature rise above ambient is approximately 120-150C. Adequate airflow or a heatsink is required; without thermal management, the device may throttle or suffer long-term reliability degradation.
コンプライアンス情報
RoHS compliant per G-suffix designation. Not AEC-Q100 qualified - this is a commercial-grade FPGA. For industrial temperature, choose I-suffix variants such as EP2AGX95EF29I5N. Halogen-free status not explicitly stated in verified data.