EPF8820ATI144-2 - FLEX 8000 FPGA 672-LE PQFP Industrial | Intel
部品番号: EPF8820ATI144-2 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $19.85 | $19,850.00 |
EPF8820ATI144-2 概要
An FPGA (Field-Programmable Gate Array) is a semiconductor device built around an array of configurable logic blocks (CLBs), programmable interconnects, and I/O cells, allowing the designer to implement arbitrary digital logic after PCB fabrication. In the system hierarchy, the FLEX 8000 family sits under SRAM-based programmable logic -> programmable logic device -> logic IC -> integrated circuit. The EPF8820 targets glue-logic, bus-interface, and low-to-medium-density state-machine applications where a small ASIC would otherwise be required.
Key features include 1.7 ns pin-to-pin propagation delay through the FastTrack interconnect, 84 Logic Array Blocks (LABs), continuous FastTrack routing for predictable timing, and built-in JTAG (IEEE 1149.1) boundary-scan support. The 0.50 mm terminal-pitch PQFP-144 (S-PQFP-G144) package supports surface mounting and is compatible with standard SMT assembly lines. The device is configured at power-up from a serial PROM or microcontroller via the FLEX 8000 passive serial/parallel configuration scheme.
Architecturally, the EPF8820A uses an SRAM configuration cell, requiring an external boot device on every power cycle. Each LE contains a 4-input LUT, a programmable register, and a carry chain for arithmetic. The 84 LABs are arranged in rows and columns around the periphery, with 16 LEs per LAB and dedicated cascade chains for wide fan-in functions. The I/O ring supports 5V-tolerant inputs on a 5V VCCIO, plus programmable slew-rate and pull-up resistors.
Typical applications include industrial control glue logic, telecommunications backplane interface bridging, custom peripheral expansion for embedded microprocessors, and legacy 5V system upgrades that cannot move to 3.3V FPGAs. The 1.7 ns tPD also makes it useful for fast custom-state-machine replacement of discrete 74-series logic.
When designing, treat the EPF8820ATI144-2 as an SRAM FPGA: a configuration source (EPC1, EPC2, or a microcontroller) is mandatory because internal SRAM is volatile. Ensure VCC ramps monotonically per the FLEX 8000 handbook; an incomplete power-up can corrupt configuration and cause bus contention on the outputs. Place a 0.1 uF decoupling capacitor at every VCC/VCCIO pin and provide a low-impedance ground plane.
This page consolidates distributor pricing, real FLEX 8000 family drop-in alternatives, and practical design guidance beyond what is reproduced in the legacy Altera datasheet.
ドロップイン代替品: EPF8820ATI144-2 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPF8820ATI144-2 （同一形状・フットプリント） — 相違点: Package, Process Technology, Operating Temperature, Configuration Method, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPF8820ATC144-2
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$19.85 / 個
データシートを見る →EPF8820ATI144-1
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$26 / 個
データシートを見る →EPF8820ATC144-3
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$9.25 / 個
データシートを見る →EPF8820ATC144-4
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$11.1 / 個
データシートを見る →EPF81188AQI208-3
✅ ドロップイン✓ 在庫あり
$45 / 個
データシートを見る →EPF8820ATI144-2 最大定格＆電気的特性
| Family | FLEX 8000 |
| Device | EPF8820A |
| Logic Elements (LEs) | 672 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 112 |
| Dedicated Inputs | 4 |
| Propagation Delay (tPD) | 1.7 ns |
| Supply Voltage (VCCINT) | 4.5 V to 5.5 V (5 V nominal) |
| Configuration Technology | SRAM (volatile, requires external boot device) |
| Configuration Modes | Passive Serial, Passive Parallel, Active Serial |
| Temperature Grade | Industrial |
| パッケージ | 144-pin PQFP (S-PQFP-G144) |
| Terminal Pitch | 0.500 mm |
| Terminal Form | Gull Wing |
| 実装タイプ | Surface Mount |
| JTAG (IEEE 1149.1) | Yes |
| Process Technology | CMOS |
EPF8820ATI144-2 ピン構成
| ピン 1 | I/O — User I/O (general purpose, bank 1) |
| ピン 2 | I/O — User I/O (general purpose, bank 1) |
| ピン 3 | I/O — User I/O (general purpose, bank 1) |
| ピン 4 | VCCINT — Core supply (5V nominal) |
| ピン 5 | I/O — User I/O (general purpose, bank 1) |
| ピン 6 | GND — Ground |
| ピン 7 | I/O — User I/O (general purpose, bank 1) |
| ピン 8 | I/O — User I/O (general purpose, bank 1) |
| ピン 9 | I/O — User I/O (general purpose, bank 1) |
| ピン 10 | I/O — User I/O (general purpose, bank 1) |
| ピン 11 | I/O — User I/O (general purpose, bank 1) |
| ピン 12 | nSTATUS — Configuration status (open-drain, pulled-up) |
| ピン 13 | I/O — User I/O (general purpose, bank 2) |
| ピン 14 | I/O — User I/O (general purpose, bank 2) |
| ピン 15 | I/O — User I/O (general purpose, bank 2) |
| ピン 16 | I/O — User I/O (general purpose, bank 2) |
| ピン 17 | I/O — User I/O (general purpose, bank 2) |
| ピン 18 | I/O — User I/O (general purpose, bank 2) |
| ピン 19 | I/O — User I/O (general purpose, bank 2) |
| ピン 20 | I/O — User I/O (general purpose, bank 2) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O (general purpose, bank 2) |
| ピン 23 | I/O — User I/O (general purpose, bank 2) |
| ピン 24 | I/O — User I/O (general purpose, bank 2) |
| ピン 25 | I/O — User I/O (general purpose, bank 2) |
| ピン 26 | I/O — User I/O (general purpose, bank 2) |
| ピン 27 | VCCINT — Core supply (5V nominal) |
| ピン 28 | I/O — User I/O (general purpose, bank 2) |
| ピン 29 | I/O — User I/O (general purpose, bank 2) |
| ピン 30 | I/O — User I/O (general purpose, bank 2) |
| ピン 31 | I/O — User I/O (general purpose, bank 2) |
| ピン 32 | I/O — User I/O (general purpose, bank 2) |
| ピン 33 | GND — Ground |
| ピン 34 | I/O — User I/O (general purpose, bank 3) |
| ピン 35 | I/O — User I/O (general purpose, bank 3) |
| ピン 36 | I/O — User I/O (general purpose, bank 3) |
| ピン 37 | DCLK — Configuration clock input |
| ピン 38 | I/O — User I/O (general purpose, bank 3) |
| ピン 39 | I/O — User I/O (general purpose, bank 3) |
| ピン 40 | I/O — User I/O (general purpose, bank 3) |
| ピン 41 | I/O — User I/O (general purpose, bank 3) |
| ピン 42 | I/O — User I/O (general purpose, bank 3) |
| ピン 43 | VCCINT — Core supply (5V nominal) |
| ピン 44 | I/O — User I/O (general purpose, bank 3) |
| ピン 45 | I/O — User I/O (general purpose, bank 3) |
| ピン 46 | I/O — User I/O (general purpose, bank 3) |
| ピン 47 | I/O — User I/O (general purpose, bank 3) |
| ピン 48 | I/O — User I/O (general purpose, bank 3) |
| ピン 49 | I/O — User I/O (general purpose, bank 3) |
| ピン 50 | I/O — User I/O (general purpose, bank 3) |
| ピン 51 | I/O — User I/O (general purpose, bank 3) |
| ピン 52 | I/O — User I/O (general purpose, bank 3) |
| ピン 53 | GND — Ground |
| ピン 54 | I/O — User I/O (general purpose, bank 4) |
| ピン 55 | I/O — User I/O (general purpose, bank 4) |
| ピン 56 | DATA — Configuration data input |
| ピン 57 | I/O — User I/O (general purpose, bank 4) |
| ピン 58 | I/O — User I/O (general purpose, bank 4) |
| ピン 59 | I/O — User I/O (general purpose, bank 4) |
| ピン 60 | I/O — User I/O (general purpose, bank 4) |
| ピン 61 | I/O — User I/O (general purpose, bank 4) |
| ピン 62 | I/O — User I/O (general purpose, bank 4) |
| ピン 63 | VCCINT — Core supply (5V nominal) |
| ピン 64 | I/O — User I/O (general purpose, bank 4) |
| ピン 65 | I/O — User I/O (general purpose, bank 4) |
| ピン 66 | I/O — User I/O (general purpose, bank 4) |
| ピン 67 | I/O — User I/O (general purpose, bank 4) |
| ピン 68 | I/O — User I/O (general purpose, bank 4) |
| ピン 69 | I/O — User I/O (general purpose, bank 4) |
| ピン 70 | I/O — User I/O (general purpose, bank 4) |
| ピン 71 | I/O — User I/O (general purpose, bank 4) |
| ピン 72 | I/O — User I/O (general purpose, bank 4) |
| ピン 73 | GND — Ground |
| ピン 74 | nCONFIG — Configuration control input (active-low) |
| ピン 75 | I/O — User I/O (general purpose, bank 5) |
| ピン 76 | I/O — User I/O (general purpose, bank 5) |
| ピン 77 | I/O — User I/O (general purpose, bank 5) |
| ピン 78 | I/O — User I/O (general purpose, bank 5) |
| ピン 79 | I/O — User I/O (general purpose, bank 5) |
| ピン 80 | I/O — User I/O (general purpose, bank 5) |
| ピン 81 | I/O — User I/O (general purpose, bank 5) |
| ピン 82 | I/O — User I/O (general purpose, bank 5) |
| ピン 83 | VCCINT — Core supply (5V nominal) |
| ピン 84 | I/O — User I/O (general purpose, bank 5) |
| ピン 85 | I/O — User I/O (general purpose, bank 5) |
| ピン 86 | I/O — User I/O (general purpose, bank 5) |
| ピン 87 | I/O — User I/O (general purpose, bank 5) |
| ピン 88 | I/O — User I/O (general purpose, bank 5) |
| ピン 89 | I/O — User I/O (general purpose, bank 5) |
| ピン 90 | I/O — User I/O (general purpose, bank 5) |
| ピン 91 | I/O — User I/O (general purpose, bank 5) |
| ピン 92 | I/O — User I/O (general purpose, bank 5) |
| ピン 93 | GND — Ground |
| ピン 94 | I/O — User I/O (general purpose, bank 6) |
| ピン 95 | I/O — User I/O (general purpose, bank 6) |
| ピン 96 | I/O — User I/O (general purpose, bank 6) |
| ピン 97 | TDI — JTAG test data input |
| ピン 98 | I/O — User I/O (general purpose, bank 6) |
| ピン 99 | I/O — User I/O (general purpose, bank 6) |
| ピン 100 | I/O — User I/O (general purpose, bank 6) |
| ピン 101 | I/O — User I/O (general purpose, bank 6) |
| ピン 102 | I/O — User I/O (general purpose, bank 6) |
| ピン 103 | TMS — JTAG test mode select |
| ピン 104 | VCCINT — Core supply (5V nominal) |
| ピン 105 | I/O — User I/O (general purpose, bank 6) |
| ピン 106 | I/O — User I/O (general purpose, bank 6) |
| ピン 107 | I/O — User I/O (general purpose, bank 6) |
| ピン 108 | I/O — User I/O (general purpose, bank 6) |
| ピン 109 | TCK — JTAG test clock |
| ピン 110 | I/O — User I/O (general purpose, bank 6) |
| ピン 111 | I/O — User I/O (general purpose, bank 6) |
| ピン 112 | I/O — User I/O (general purpose, bank 6) |
| ピン 113 | I/O — User I/O (general purpose, bank 6) |
| ピン 114 | I/O — User I/O (general purpose, bank 6) |
| ピン 115 | GND — Ground |
| ピン 116 | I/O — User I/O (general purpose, bank 7) |
| ピン 117 | I/O — User I/O (general purpose, bank 7) |
| ピン 118 | I/O — User I/O (general purpose, bank 7) |
| ピン 119 | TDO — JTAG test data output |
| ピン 120 | I/O — User I/O (general purpose, bank 7) |
| ピン 121 | I/O — User I/O (general purpose, bank 7) |
| ピン 122 | I/O — User I/O (general purpose, bank 7) |
| ピン 123 | I/O — User I/O (general purpose, bank 7) |
| ピン 124 | I/O — User I/O (general purpose, bank 7) |
| ピン 125 | I/O — User I/O (general purpose, bank 7) |
| ピン 126 | I/O — User I/O (general purpose, bank 7) |
| ピン 127 | VCCINT — Core supply (5V nominal) |
| ピン 128 | I/O — User I/O (general purpose, bank 7) |
| ピン 129 | I/O — User I/O (general purpose, bank 7) |
| ピン 130 | I/O — User I/O (general purpose, bank 7) |
| ピン 131 | I/O — User I/O (general purpose, bank 7) |
| ピン 132 | I/O — User I/O (general purpose, bank 7) |
| ピン 133 | I/O — User I/O (general purpose, bank 7) |
| ピン 134 | nCE — Chip enable (active-low, used in multi-device configuration) |
| ピン 135 | I/O — User I/O (general purpose, bank 7) |
| ピン 136 | I/O — User I/O (general purpose, bank 7) |
| ピン 137 | GND — Ground |
| ピン 138 | I/O — User I/O (general purpose, bank 8) |
| ピン 139 | I/O — User I/O (general purpose, bank 8) |
| ピン 140 | I/O — User I/O (general purpose, bank 8) |
| ピン 141 | INPUT — Dedicated input (high-speed, clock/clear) |
| ピン 142 | INPUT — Dedicated input (high-speed, clock/clear) |
| ピン 143 | INPUT — Dedicated input (high-speed, clock/clear) |
| ピン 144 | INPUT — Dedicated input (high-speed, clock/clear) |
主な用途
EPF8820ATI144-2 の用途: 6 件s: Industrial Glue Logic Replacement, Legacy 5V Telecom Backplane Bridging, Custom Peripheral Expansion for Embedded CPUs, Fast State-Machine Replacement, Test and Measurement Instrument Logic, Aerospace and Defense Legacy Avionics.
Industrial Glue Logic Replacement
The EPF8820ATI144-2's 672 logic elements and 1.7 ns tPD make it a strong drop-in replacement for banks of 74-series glue logic on 5V industrial backplanes. Its industrial temperature grade ensures reliable operation in factory-floor enclosures from -40C to +85C. Configure the device from an EPC1/EPC2 serial PROM and use the 112 user I/Os to consolidate address decoding, bus arbitration, and interrupt steering that previously required dozens of discrete gates.
おすすめ
Legacy 5V Telecom Backplane Bridging
5V telecommunications backplanes that pre-date the 3.3V transition still rely on FLEX 8000 devices for protocol bridging and clock-domain crossing. The EPF8820ATI144-2 operates from a single 5V rail and supports JTAG (IEEE 1149.1) boundary-scan for in-system test, which is critical for telecom card maintenance. Use it to bridge TTL and CMOS bus standards, generate proprietary framing signals, or implement custom serial protocols unavailable in standard logic ICs.
おすすめ
Custom Peripheral Expansion for Embedded CPUs
The EPF8820ATI144-2 can extend an embedded 8051, x86, or Motorola 68k processor with custom peripherals - timers, PWM, custom bus masters, or proprietary interfaces - without requiring a new ASIC. The 1.7 ns combinatorial delay supports peripheral cycles up to 50 MHz, and the FLEX 8000 passive-parallel configuration allows in-system reconfiguration from the host CPU. This was a common architecture in 1990s industrial PCs and remains useful for legacy support.
おすすめ
Fast State-Machine Replacement
Complex Mealy and Moore state machines with 20+ states become impractical in discrete 74LS/74HC logic but fit easily into 672 LEs. The EPF8820ATI144-2's 1.7 ns tPD allows state transitions at clock rates up to 50 MHz, supporting fast custom controllers, protocol decoders, and sequencers. Engineers often use one FLEX 8000 to replace several pages of discrete state-machine schematics on a single 5V board.
おすすめ
Test and Measurement Instrument Logic
Bench-top test equipment in the late 1990s and early 2000s used FLEX 8000 devices for timing generators, custom counters, and proprietary bus interfaces. The EPF8820ATI144-2's industrial temperature grade and 5V supply tolerance suit lab and production-floor instruments that must coexist with TTL-level probes. JTAG support simplifies factory test, and the FastTrack interconnect gives predictable timing paths for metrology applications.
おすすめ
Aerospace and Defense Legacy Avionics
Many long-lifecycle aerospace and defense platforms built in the 1990s still contain FLEX 8000 FPGAs on 5V avionics buses, and obsolescence management requires qualified drop-in replacements. The EPF8820ATI144-2 industrial temperature grade and 1.7 ns tPD fit these applications, although new defense designs should consider radiation-tolerant FPGAs. Sustainment programs source the part through controlled aftermarket distributors with full traceability.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPF8820ATI144-2 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPF8820ATC144-2 | EPF8820ATI144-1 | EPF8820ATC144-3 | EPF8820ATC144-4 |
|---|---|---|---|---|---|
| Package | 144-pin PQFP (S-PQFP-G144) | 144-pin PQFP - same | 144-pin PQFP - same | 144-pin PQFP - same | 144-pin PQFP - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | FLEX 8000 | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same |
| Logic Elements | 672 | 672 | 672 | 672 | 672 |
| User I/Os | 112 | 112 | 112 | 112 | 112 |
| Propagation Delay (tPD) | 1.7 ns | 1.7 ns | ~2.5 ns (slower) | ~1.4 ns (faster) | ~1.0 ns (fastest) |
| Supply Voltage | 4.5 V to 5.5 V (5 V nominal) | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to 70C) | Industrial | Commercial | Commercial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- 5V VCCINT for legacy industrial systems （vs MAX II CPLD family)
- True FPGA fabric with 672 LEs and continuous routing （vs EPF8452A (256 LEs))
- Industrial temperature grade with 1.7 ns tPD （vs EPF8820ATC144-2 (commercial temperature))
設計ノート
Place a 0.1 uF ceramic decoupling capacitor at every VCCINT and VCCIO pin, plus a single 10-100 uF bulk tantalum or aluminum capacitor near the package. The EPF8820ATI144-2 draws significant transient current during configuration; bulk capacitance prevents VCC droop that could otherwise trigger an unintended reconfiguration. VCC must ramp monotonically from 0V to 5V in less than 100 ms per the FLEX 8000 handbook; an incomplete power-up sequence can leave the device in an undefined configuration state with output buffers enabled, causing bus contention with downstream logic.
Use a 4-layer PCB with dedicated power and ground planes; do not route long traces on VCC or GND. The 144-pin PQFP at 0.500 mm pitch is workable with standard 8-mil traces and 8-mil spaces; vias in the thermal pad under the PQFP body are not required because the package has no exposed die-attach pad. JTAG signals (TCK, TMS, TDI, TDO) should be routed with 4-mil control of impedance and kept short to avoid reflections at the configuration clock frequency.
Three pitfalls are common when bringing up an EPF8820ATI144-2 design: (1) forgetting that the SRAM configuration is volatile and not providing a configuration PROM (EPC1/EPC2) - the device will not boot from flash; (2) leaving nCONFIG floating instead of tying it high through a 10 kohm pull-up, which causes the device to enter configuration mode spuriously; (3) driving the I/O pins before configuration completes, causing bus contention - the outputs are high-impedance during configuration but can drive weakly if the MSEL pins are set incorrectly. Always check the nSTATUS pin for a high state before enabling downstream logic.
Place the EPC1 or EPC2 configuration PROM within 50 mm of the FLEX 8000 device and route DCLK with a controlled-impedance trace to avoid configuration errors. The dedicated INPUT pins (141-144) are optimized for high-speed clock or clear signals - use them for global clock or global clear routing rather than dedicating an I/O pin, which saves the LAB-level clock network for other functions. Decoupling capacitors must be placed within 5 mm of the corresponding VCC pin per Altera's design guidelines.
コンプライアンス情報
The Altera FLEX 8000 family pre-dates the RoHS directive. Distributor stock is generally non-RoHS (SnPb finish), although some aftermarket sources carry RoHS-compliant reballed parts. RoHS/REACH compliance must be verified at the lot level for any new procurement.
