EPF8820ATI144-2 - FLEX 8000 FPGA 672-LE PQFP Industrial | Intel
MPN: EPF8820ATI144-2 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $22.1 | $11,050.00 |
| 1,000 | $19.85 | $19,850.00 |
Drop-in alternatives for EPF8820ATI144-2 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPF8820ATC144-2
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPF8820ATI144-1
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View Datasheet βEPF8820ATC144-3
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View Datasheet βEPF8820ATC144-4
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View Datasheet βEPF8820ATI144-2 Maximum Ratings & Electrical Characteristics
| Family | FLEX 8000 |
| Device | EPF8820A |
| Logic Elements (LEs) | 672 |
| Logic Array Blocks (LABs) | 84 |
| User I/Os | 112 |
| Dedicated Inputs | 4 |
| Propagation Delay (tPD) | 1.7 ns |
| Supply Voltage (VCCINT) | 4.5 V to 5.5 V (5 V nominal) |
| Configuration Technology | SRAM (volatile, requires external boot device) |
| Configuration Modes | Passive Serial, Passive Parallel, Active Serial |
| Temperature Grade | Industrial |
| Package | 144-pin PQFP (S-PQFP-G144) |
| Terminal Pitch | 0.500 mm |
| Terminal Form | Gull Wing |
| Mounting Type | Surface Mount |
| JTAG (IEEE 1149.1) | Yes |
| Process Technology | CMOS |
EPF8820ATI144-2 Pin Configuration
| Pin 1 | I/O β User I/O (general purpose, bank 1) |
| Pin 2 | I/O β User I/O (general purpose, bank 1) |
| Pin 3 | I/O β User I/O (general purpose, bank 1) |
| Pin 4 | VCCINT β Core supply (5V nominal) |
| Pin 5 | I/O β User I/O (general purpose, bank 1) |
| Pin 6 | GND β Ground |
| Pin 7 | I/O β User I/O (general purpose, bank 1) |
| Pin 8 | I/O β User I/O (general purpose, bank 1) |
| Pin 9 | I/O β User I/O (general purpose, bank 1) |
| Pin 10 | I/O β User I/O (general purpose, bank 1) |
| Pin 11 | I/O β User I/O (general purpose, bank 1) |
| Pin 12 | nSTATUS β Configuration status (open-drain, pulled-up) |
| Pin 13 | I/O β User I/O (general purpose, bank 2) |
| Pin 14 | I/O β User I/O (general purpose, bank 2) |
| Pin 15 | I/O β User I/O (general purpose, bank 2) |
| Pin 16 | I/O β User I/O (general purpose, bank 2) |
| Pin 17 | I/O β User I/O (general purpose, bank 2) |
| Pin 18 | I/O β User I/O (general purpose, bank 2) |
| Pin 19 | I/O β User I/O (general purpose, bank 2) |
| Pin 20 | I/O β User I/O (general purpose, bank 2) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (general purpose, bank 2) |
| Pin 23 | I/O β User I/O (general purpose, bank 2) |
| Pin 24 | I/O β User I/O (general purpose, bank 2) |
| Pin 25 | I/O β User I/O (general purpose, bank 2) |
| Pin 26 | I/O β User I/O (general purpose, bank 2) |
| Pin 27 | VCCINT β Core supply (5V nominal) |
| Pin 28 | I/O β User I/O (general purpose, bank 2) |
| Pin 29 | I/O β User I/O (general purpose, bank 2) |
| Pin 30 | I/O β User I/O (general purpose, bank 2) |
| Pin 31 | I/O β User I/O (general purpose, bank 2) |
| Pin 32 | I/O β User I/O (general purpose, bank 2) |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β User I/O (general purpose, bank 3) |
| Pin 35 | I/O β User I/O (general purpose, bank 3) |
| Pin 36 | I/O β User I/O (general purpose, bank 3) |
| Pin 37 | DCLK β Configuration clock input |
| Pin 38 | I/O β User I/O (general purpose, bank 3) |
| Pin 39 | I/O β User I/O (general purpose, bank 3) |
| Pin 40 | I/O β User I/O (general purpose, bank 3) |
| Pin 41 | I/O β User I/O (general purpose, bank 3) |
| Pin 42 | I/O β User I/O (general purpose, bank 3) |
| Pin 43 | VCCINT β Core supply (5V nominal) |
| Pin 44 | I/O β User I/O (general purpose, bank 3) |
| Pin 45 | I/O β User I/O (general purpose, bank 3) |
| Pin 46 | I/O β User I/O (general purpose, bank 3) |
| Pin 47 | I/O β User I/O (general purpose, bank 3) |
| Pin 48 | I/O β User I/O (general purpose, bank 3) |
| Pin 49 | I/O β User I/O (general purpose, bank 3) |
| Pin 50 | I/O β User I/O (general purpose, bank 3) |
| Pin 51 | I/O β User I/O (general purpose, bank 3) |
| Pin 52 | I/O β User I/O (general purpose, bank 3) |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β User I/O (general purpose, bank 4) |
| Pin 55 | I/O β User I/O (general purpose, bank 4) |
| Pin 56 | DATA β Configuration data input |
| Pin 57 | I/O β User I/O (general purpose, bank 4) |
| Pin 58 | I/O β User I/O (general purpose, bank 4) |
| Pin 59 | I/O β User I/O (general purpose, bank 4) |
| Pin 60 | I/O β User I/O (general purpose, bank 4) |
| Pin 61 | I/O β User I/O (general purpose, bank 4) |
| Pin 62 | I/O β User I/O (general purpose, bank 4) |
| Pin 63 | VCCINT β Core supply (5V nominal) |
| Pin 64 | I/O β User I/O (general purpose, bank 4) |
| Pin 65 | I/O β User I/O (general purpose, bank 4) |
| Pin 66 | I/O β User I/O (general purpose, bank 4) |
| Pin 67 | I/O β User I/O (general purpose, bank 4) |
| Pin 68 | I/O β User I/O (general purpose, bank 4) |
| Pin 69 | I/O β User I/O (general purpose, bank 4) |
| Pin 70 | I/O β User I/O (general purpose, bank 4) |
| Pin 71 | I/O β User I/O (general purpose, bank 4) |
| Pin 72 | I/O β User I/O (general purpose, bank 4) |
| Pin 73 | GND β Ground |
| Pin 74 | nCONFIG β Configuration control input (active-low) |
| Pin 75 | I/O β User I/O (general purpose, bank 5) |
| Pin 76 | I/O β User I/O (general purpose, bank 5) |
| Pin 77 | I/O β User I/O (general purpose, bank 5) |
| Pin 78 | I/O β User I/O (general purpose, bank 5) |
| Pin 79 | I/O β User I/O (general purpose, bank 5) |
| Pin 80 | I/O β User I/O (general purpose, bank 5) |
| Pin 81 | I/O β User I/O (general purpose, bank 5) |
| Pin 82 | I/O β User I/O (general purpose, bank 5) |
| Pin 83 | VCCINT β Core supply (5V nominal) |
| Pin 84 | I/O β User I/O (general purpose, bank 5) |
| Pin 85 | I/O β User I/O (general purpose, bank 5) |
| Pin 86 | I/O β User I/O (general purpose, bank 5) |
| Pin 87 | I/O β User I/O (general purpose, bank 5) |
| Pin 88 | I/O β User I/O (general purpose, bank 5) |
| Pin 89 | I/O β User I/O (general purpose, bank 5) |
| Pin 90 | I/O β User I/O (general purpose, bank 5) |
| Pin 91 | I/O β User I/O (general purpose, bank 5) |
| Pin 92 | I/O β User I/O (general purpose, bank 5) |
| Pin 93 | GND β Ground |
| Pin 94 | I/O β User I/O (general purpose, bank 6) |
| Pin 95 | I/O β User I/O (general purpose, bank 6) |
| Pin 96 | I/O β User I/O (general purpose, bank 6) |
| Pin 97 | TDI β JTAG test data input |
| Pin 98 | I/O β User I/O (general purpose, bank 6) |
| Pin 99 | I/O β User I/O (general purpose, bank 6) |
| Pin 100 | I/O β User I/O (general purpose, bank 6) |
| Pin 101 | I/O β User I/O (general purpose, bank 6) |
| Pin 102 | I/O β User I/O (general purpose, bank 6) |
| Pin 103 | TMS β JTAG test mode select |
| Pin 104 | VCCINT β Core supply (5V nominal) |
| Pin 105 | I/O β User I/O (general purpose, bank 6) |
| Pin 106 | I/O β User I/O (general purpose, bank 6) |
| Pin 107 | I/O β User I/O (general purpose, bank 6) |
| Pin 108 | I/O β User I/O (general purpose, bank 6) |
| Pin 109 | TCK β JTAG test clock |
| Pin 110 | I/O β User I/O (general purpose, bank 6) |
| Pin 111 | I/O β User I/O (general purpose, bank 6) |
| Pin 112 | I/O β User I/O (general purpose, bank 6) |
| Pin 113 | I/O β User I/O (general purpose, bank 6) |
| Pin 114 | I/O β User I/O (general purpose, bank 6) |
| Pin 115 | GND β Ground |
| Pin 116 | I/O β User I/O (general purpose, bank 7) |
| Pin 117 | I/O β User I/O (general purpose, bank 7) |
| Pin 118 | I/O β User I/O (general purpose, bank 7) |
| Pin 119 | TDO β JTAG test data output |
| Pin 120 | I/O β User I/O (general purpose, bank 7) |
| Pin 121 | I/O β User I/O (general purpose, bank 7) |
| Pin 122 | I/O β User I/O (general purpose, bank 7) |
| Pin 123 | I/O β User I/O (general purpose, bank 7) |
| Pin 124 | I/O β User I/O (general purpose, bank 7) |
| Pin 125 | I/O β User I/O (general purpose, bank 7) |
| Pin 126 | I/O β User I/O (general purpose, bank 7) |
| Pin 127 | VCCINT β Core supply (5V nominal) |
| Pin 128 | I/O β User I/O (general purpose, bank 7) |
| Pin 129 | I/O β User I/O (general purpose, bank 7) |
| Pin 130 | I/O β User I/O (general purpose, bank 7) |
| Pin 131 | I/O β User I/O (general purpose, bank 7) |
| Pin 132 | I/O β User I/O (general purpose, bank 7) |
| Pin 133 | I/O β User I/O (general purpose, bank 7) |
| Pin 134 | nCE β Chip enable (active-low, used in multi-device configuration) |
| Pin 135 | I/O β User I/O (general purpose, bank 7) |
| Pin 136 | I/O β User I/O (general purpose, bank 7) |
| Pin 137 | GND β Ground |
| Pin 138 | I/O β User I/O (general purpose, bank 8) |
| Pin 139 | I/O β User I/O (general purpose, bank 8) |
| Pin 140 | I/O β User I/O (general purpose, bank 8) |
| Pin 141 | INPUT β Dedicated input (high-speed, clock/clear) |
| Pin 142 | INPUT β Dedicated input (high-speed, clock/clear) |
| Pin 143 | INPUT β Dedicated input (high-speed, clock/clear) |
| Pin 144 | INPUT β Dedicated input (high-speed, clock/clear) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPF8820ATI144-2 is suitable for 6 applications: Industrial Glue Logic Replacement, Legacy 5V Telecom Backplane Bridging, Custom Peripheral Expansion for Embedded CPUs, Fast State-Machine Replacement, Test and Measurement Instrument Logic, Aerospace and Defense Legacy Avionics.
Industrial Glue Logic Replacement
The EPF8820ATI144-2's 672 logic elements and 1.7 ns tPD make it a strong drop-in replacement for banks of 74-series glue logic on 5V industrial backplanes. Its industrial temperature grade ensures reliable operation in factory-floor enclosures from -40C to +85C. Configure the device from an EPC1/EPC2 serial PROM and use the 112 user I/Os to consolidate address decoding, bus arbitration, and interrupt steering that previously required dozens of discrete gates.
Recommended
Legacy 5V Telecom Backplane Bridging
5V telecommunications backplanes that pre-date the 3.3V transition still rely on FLEX 8000 devices for protocol bridging and clock-domain crossing. The EPF8820ATI144-2 operates from a single 5V rail and supports JTAG (IEEE 1149.1) boundary-scan for in-system test, which is critical for telecom card maintenance. Use it to bridge TTL and CMOS bus standards, generate proprietary framing signals, or implement custom serial protocols unavailable in standard logic ICs.
Recommended
Custom Peripheral Expansion for Embedded CPUs
The EPF8820ATI144-2 can extend an embedded 8051, x86, or Motorola 68k processor with custom peripherals - timers, PWM, custom bus masters, or proprietary interfaces - without requiring a new ASIC. The 1.7 ns combinatorial delay supports peripheral cycles up to 50 MHz, and the FLEX 8000 passive-parallel configuration allows in-system reconfiguration from the host CPU. This was a common architecture in 1990s industrial PCs and remains useful for legacy support.
Recommended
Fast State-Machine Replacement
Complex Mealy and Moore state machines with 20+ states become impractical in discrete 74LS/74HC logic but fit easily into 672 LEs. The EPF8820ATI144-2's 1.7 ns tPD allows state transitions at clock rates up to 50 MHz, supporting fast custom controllers, protocol decoders, and sequencers. Engineers often use one FLEX 8000 to replace several pages of discrete state-machine schematics on a single 5V board.
Recommended
Test and Measurement Instrument Logic
Bench-top test equipment in the late 1990s and early 2000s used FLEX 8000 devices for timing generators, custom counters, and proprietary bus interfaces. The EPF8820ATI144-2's industrial temperature grade and 5V supply tolerance suit lab and production-floor instruments that must coexist with TTL-level probes. JTAG support simplifies factory test, and the FastTrack interconnect gives predictable timing paths for metrology applications.
Recommended
Aerospace and Defense Legacy Avionics
Many long-lifecycle aerospace and defense platforms built in the 1990s still contain FLEX 8000 FPGAs on 5V avionics buses, and obsolescence management requires qualified drop-in replacements. The EPF8820ATI144-2 industrial temperature grade and 1.7 ns tPD fit these applications, although new defense designs should consider radiation-tolerant FPGAs. Sustainment programs source the part through controlled aftermarket distributors with full traceability.
Recommended
Recommended Products Summary
Engineering reference data for EPF8820ATI144-2 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPF8820ATC144-2 | EPF8820ATI144-1 | EPF8820ATC144-3 | EPF8820ATC144-4 |
|---|---|---|---|---|---|
| Package | 144-pin PQFP (S-PQFP-G144) | 144-pin PQFP - same | 144-pin PQFP - same | 144-pin PQFP - same | 144-pin PQFP - same |
| Brand | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) | Intel (formerly Altera) |
| Family | FLEX 8000 | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same | FLEX 8000 - same |
| Logic Elements | 672 | 672 | 672 | 672 | 672 |
| User I/Os | 112 | 112 | 112 | 112 | 112 |
| Propagation Delay (tPD) | 1.7 ns | 1.7 ns | ~2.5 ns (slower) | ~1.4 ns (faster) | ~1.0 ns (fastest) |
| Supply Voltage | 4.5 V to 5.5 V (5 V nominal) | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V | 4.5 V to 5.5 V |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to 70C) | Industrial | Commercial | Commercial |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- 5V VCCINT for legacy industrial systems (vs MAX II CPLD family)
- True FPGA fabric with 672 LEs and continuous routing (vs EPF8452A (256 LEs))
- Industrial temperature grade with 1.7 ns tPD (vs EPF8820ATC144-2 (commercial temperature))
Design Notes
Place a 0.1 uF ceramic decoupling capacitor at every VCCINT and VCCIO pin, plus a single 10-100 uF bulk tantalum or aluminum capacitor near the package. The EPF8820ATI144-2 draws significant transient current during configuration; bulk capacitance prevents VCC droop that could otherwise trigger an unintended reconfiguration. VCC must ramp monotonically from 0V to 5V in less than 100 ms per the FLEX 8000 handbook; an incomplete power-up sequence can leave the device in an undefined configuration state with output buffers enabled, causing bus contention with downstream logic.
Use a 4-layer PCB with dedicated power and ground planes; do not route long traces on VCC or GND. The 144-pin PQFP at 0.500 mm pitch is workable with standard 8-mil traces and 8-mil spaces; vias in the thermal pad under the PQFP body are not required because the package has no exposed die-attach pad. JTAG signals (TCK, TMS, TDI, TDO) should be routed with 4-mil control of impedance and kept short to avoid reflections at the configuration clock frequency.
Three pitfalls are common when bringing up an EPF8820ATI144-2 design: (1) forgetting that the SRAM configuration is volatile and not providing a configuration PROM (EPC1/EPC2) - the device will not boot from flash; (2) leaving nCONFIG floating instead of tying it high through a 10 kohm pull-up, which causes the device to enter configuration mode spuriously; (3) driving the I/O pins before configuration completes, causing bus contention - the outputs are high-impedance during configuration but can drive weakly if the MSEL pins are set incorrectly. Always check the nSTATUS pin for a high state before enabling downstream logic.
Place the EPC1 or EPC2 configuration PROM within 50 mm of the FLEX 8000 device and route DCLK with a controlled-impedance trace to avoid configuration errors. The dedicated INPUT pins (141-144) are optimized for high-speed clock or clear signals - use them for global clock or global clear routing rather than dedicating an I/O pin, which saves the LAB-level clock network for other functions. Decoupling capacitors must be placed within 5 mm of the corresponding VCC pin per Altera's design guidelines.
Compliance Information
The Altera FLEX 8000 family pre-dates the RoHS directive. Distributor stock is generally non-RoHS (SnPb finish), although some aftermarket sources carry RoHS-compliant reballed parts. RoHS/REACH compliance must be verified at the lot level for any new procurement.
