EPM3128ATI144-5N - 128-Macrocell 2.5K CPLD MAX 3000A | Altera
部品番号: EPM3128ATI144-5N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.5 | $10,500.00 |
EPM3128ATI144-5N 概要
What is a CPLD? A Complex Programmable Logic Device is a non-volatile, instantly-on programmable logic IC that combines multiple PAL-style macrocell arrays on a single die with a central interconnect matrix. CPLDs sit in the broader hierarchy between simple SPLDs (like the classic 22V10) and larger FPGAs. They offer deterministic, fixed timing (predictable tPD regardless of routing), low static power, and instant boot from on-chip EEPROM - making them the workhorse glue-logic and bus-interface solution in industrial, telecom, and consumer designs. The MAX 3000A family is Altera's classic 3.3 V EEPROM-based CPLD line.
Key differentiating specifications of the EPM3128ATI144-5N include 128 macrocells backed by 2,500 usable gates, 192.3 MHz fMAX with 5.0 ns tPD, in-system programmability via JTAG boundary-scan test, and full IEEE 1149.1 boundary-scan support. Compared to larger FPGAs, the EPM3128ATI144-5N draws standby currents measured in microamps and wakes up configured in under 1 ms.
Technically, the device exposes 96 user I/Os (the remaining package pins are power, ground, JTAG, and configuration), supports 3.3 V LVCMOS/LVTTL I/O with 5.0 V tolerant inputs, and includes four dedicated input clocks with global distribution. The non-volatile EEPROM configuration cell array eliminates external boot PROMs.
Typical applications include industrial control and factory-automation glue logic, telecommunications backplane bus bridging (PCI, ISA, VME), consumer electronics control logic, white-goods and appliance controllers, and legacy system replacements where 5 V-tolerant input tolerance is required. Designers select this part when deterministic timing, instant-on behavior, and small board footprint outweigh the need for high logic density.
When designing with the EPM3128ATI144-5N, observe the 3.0 V to 3.6 V supply rail tolerance and decouple each VCCIO/VCCINT pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin. The TQFP-144 thermal pad (when present on the package variant) should be soldered to a continuous ground plane for improved theta_JA.
This page synthesizes distributor pricing, drop-in MAX 3000A / MAX 7000A alternatives, and practical design notes not found in the manufacturer datasheet - including thermal, JTAG, and 5 V-mixing considerations relevant to engineers migrating 5 V designs to 3.3 V.
ドロップイン代替品: EPM3128ATI144-5N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM3128ATI144-5N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, RoHS Status, Mounting Type, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
EPM3128ATI144-10N
✅ ドロップイン✓ 在庫あり
$10.32 / 個
データシートを見る →EPM3128ATC144-5N
✅ ドロップイン✓ 在庫あり
$13.75 / 個
データシートを見る →EPM3128ATC144-10N
✅ ドロップイン✓ 在庫あり
$6.56 / 個
データシートを見る →EPM3128ATC144-7N
✅ ドロップイン✓ 在庫あり
$9.25 / 個
データシートを見る →EPM3128ATI144-10
✅ ドロップイン✓ 在庫あり
$10.85 / 個
データシートを見る →EPM3128ATI144-5N 最大定格＆電気的特性
| Family | MAX 3000A |
| Logic Gates | 2,500 gates |
| Macro Cells | 128 |
| User I/Os | 96 |
| Maximum Operating Frequency | 192.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.0 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Standard | LVCMOS / LVTTL (5.0 V tolerant inputs) |
| Programming Interface | JTAG (IEEE 1149.1 BST) - in-system |
| Process Technology | 0.30 um CMOS EEPROM |
| Configuration Memory | Non-volatile on-chip EEPROM |
| パッケージ | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40C to +85C (industrial) |
| MSLレベル | 3 (168 hours) |
EPM3128ATI144-5N ピン構成
| ピン 1 | I/O — User I/O pin (group 1, bank 1) |
| ピン 2 | I/O — User I/O pin (group 1, bank 1) |
| ピン 3 | I/O — User I/O pin (group 1, bank 1) |
| ピン 4 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 5 | I/O — User I/O pin (group 1, bank 1) |
| ピン 6 | I/O — User I/O pin (group 1, bank 1) |
| ピン 7 | I/O — User I/O pin (group 1, bank 1) |
| ピン 8 | GND — Ground |
| ピン 9 | I/O — User I/O pin (group 1, bank 2) |
| ピン 10 | I/O — User I/O pin (group 1, bank 2) |
| ピン 11 | I/O — User I/O pin (group 1, bank 2) |
| ピン 12 | VCCINT — Core supply voltage (3.3 V) |
| ピン 13 | I/O — User I/O pin (group 1, bank 2) |
| ピン 14 | I/O — User I/O pin (group 1, bank 2) |
| ピン 15 | I/O — User I/O pin (group 1, bank 2) |
| ピン 16 | GND — Ground |
| ピン 17 | I/O — User I/O pin (group 1, bank 2) |
| ピン 18 | I/O — User I/O pin (group 1, bank 2) |
| ピン 19 | I/O — User I/O pin (group 1, bank 2) |
| ピン 20 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 21 | I/O — User I/O pin (group 1, bank 2) |
| ピン 22 | I/O — User I/O pin (group 1, bank 2) |
| ピン 23 | I/O — User I/O pin (group 1, bank 2) |
| ピン 24 | GND — Ground |
| ピン 25 | I/O — User I/O pin (group 1, bank 2) |
| ピン 26 | I/O — User I/O pin (group 1, bank 2) |
| ピン 27 | I/O — User I/O pin (group 1, bank 2) |
| ピン 28 | INPUT/GCLK1 — Dedicated input / global clock 1 |
| ピン 29 | INPUT/GCLK3 — Dedicated input / global clock 3 |
| ピン 30 | I/O — User I/O pin (group 2, bank 3) |
| ピン 31 | I/O — User I/O pin (group 2, bank 3) |
| ピン 32 | I/O — User I/O pin (group 2, bank 3) |
| ピン 33 | GND — Ground |
| ピン 34 | I/O — User I/O pin (group 2, bank 3) |
| ピン 35 | I/O — User I/O pin (group 2, bank 3) |
| ピン 36 | I/O — User I/O pin (group 2, bank 3) |
| ピン 37 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 38 | I/O — User I/O pin (group 2, bank 3) |
| ピン 39 | I/O — User I/O pin (group 2, bank 3) |
| ピン 40 | I/O — User I/O pin (group 2, bank 3) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (group 2, bank 3) |
| ピン 43 | I/O — User I/O pin (group 2, bank 3) |
| ピン 44 | I/O — User I/O pin (group 2, bank 3) |
| ピン 45 | VCCINT — Core supply voltage (3.3 V) |
| ピン 46 | I/O — User I/O pin (group 2, bank 3) |
| ピン 47 | I/O — User I/O pin (group 2, bank 3) |
| ピン 48 | I/O — User I/O pin (group 2, bank 3) |
| ピン 49 | GND — Ground |
| ピン 50 | I/O — User I/O pin (group 2, bank 3) |
| ピン 51 | I/O — User I/O pin (group 2, bank 3) |
| ピン 52 | I/O — User I/O pin (group 2, bank 3) |
| ピン 53 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 54 | I/O — User I/O pin (group 2, bank 3) |
| ピン 55 | I/O — User I/O pin (group 2, bank 3) |
| ピン 56 | I/O — User I/O pin (group 2, bank 3) |
| ピン 57 | GND — Ground |
| ピン 58 | I/O — User I/O pin (group 2, bank 3) |
| ピン 59 | I/O — User I/O pin (group 2, bank 3) |
| ピン 60 | I/O — User I/O pin (group 2, bank 3) |
| ピン 61 | INPUT/GCLK2 — Dedicated input / global clock 2 |
| ピン 62 | INPUT/GCLK4 — Dedicated input / global clock 4 |
| ピン 63 | I/O — User I/O pin (group 3, bank 4) |
| ピン 64 | I/O — User I/O pin (group 3, bank 4) |
| ピン 65 | I/O — User I/O pin (group 3, bank 4) |
| ピン 66 | GND — Ground |
| ピン 67 | I/O — User I/O pin (group 3, bank 4) |
| ピン 68 | I/O — User I/O pin (group 3, bank 4) |
| ピン 69 | I/O — User I/O pin (group 3, bank 4) |
| ピン 70 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 71 | I/O — User I/O pin (group 3, bank 4) |
| ピン 72 | I/O — User I/O pin (group 3, bank 4) |
| ピン 73 | I/O — User I/O pin (group 3, bank 4) |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — User I/O pin (group 3, bank 4) |
| ピン 76 | I/O — User I/O pin (group 3, bank 4) |
| ピン 77 | I/O — User I/O pin (group 3, bank 4) |
| ピン 78 | VCCINT — Core supply voltage (3.3 V) |
| ピン 79 | I/O — User I/O pin (group 3, bank 4) |
| ピン 80 | I/O — User I/O pin (group 3, bank 4) |
| ピン 81 | I/O — User I/O pin (group 3, bank 4) |
| ピン 82 | GND — Ground |
| ピン 83 | I/O — User I/O pin (group 3, bank 4) |
| ピン 84 | I/O — User I/O pin (group 3, bank 4) |
| ピン 85 | I/O — User I/O pin (group 3, bank 4) |
| ピン 86 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 87 | I/O — User I/O pin (group 3, bank 4) |
| ピン 88 | I/O — User I/O pin (group 3, bank 4) |
| ピン 89 | I/O — User I/O pin (group 3, bank 4) |
| ピン 90 | GND — Ground |
| ピン 91 | I/O — User I/O pin (group 3, bank 4) |
| ピン 92 | I/O — User I/O pin (group 3, bank 4) |
| ピン 93 | I/O — User I/O pin (group 3, bank 4) |
| ピン 94 | TDI — JTAG test data input |
| ピン 95 | TMS — JTAG test mode select |
| ピン 96 | TCK — JTAG test clock |
| ピン 97 | NC — Not connected (per datasheet) |
| ピン 98 | NC — Not connected (per datasheet) |
| ピン 99 | NC — Not connected (per datasheet) |
| ピン 100 | TDO — JTAG test data output |
| ピン 101 | I/O — User I/O pin (group 4, bank 1) |
| ピン 102 | I/O — User I/O pin (group 4, bank 1) |
| ピン 103 | I/O — User I/O pin (group 4, bank 1) |
| ピン 104 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 105 | I/O — User I/O pin (group 4, bank 1) |
| ピン 106 | I/O — User I/O pin (group 4, bank 1) |
| ピン 107 | I/O — User I/O pin (group 4, bank 1) |
| ピン 108 | GND — Ground |
| ピン 109 | I/O — User I/O pin (group 4, bank 1) |
| ピン 110 | I/O — User I/O pin (group 4, bank 1) |
| ピン 111 | I/O — User I/O pin (group 4, bank 1) |
| ピン 112 | VCCINT — Core supply voltage (3.3 V) |
| ピン 113 | I/O — User I/O pin (group 4, bank 1) |
| ピン 114 | I/O — User I/O pin (group 4, bank 1) |
| ピン 115 | I/O — User I/O pin (group 4, bank 1) |
| ピン 116 | GND — Ground |
| ピン 117 | I/O — User I/O pin (group 4, bank 1) |
| ピン 118 | I/O — User I/O pin (group 4, bank 1) |
| ピン 119 | I/O — User I/O pin (group 4, bank 1) |
| ピン 120 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 121 | I/O — User I/O pin (group 4, bank 1) |
| ピン 122 | I/O — User I/O pin (group 4, bank 1) |
| ピン 123 | I/O — User I/O pin (group 4, bank 1) |
| ピン 124 | GND — Ground |
| ピン 125 | I/O — User I/O pin (group 4, bank 1) |
| ピン 126 | I/O — User I/O pin (group 4, bank 1) |
| ピン 127 | I/O — User I/O pin (group 4, bank 1) |
| ピン 128 | INPUT/OE — Dedicated input / output enable |
| ピン 129 | INPUT/CLR — Dedicated input / clear |
| ピン 130 | I/O — User I/O pin (group 1, bank 1) |
| ピン 131 | I/O — User I/O pin (group 1, bank 1) |
| ピン 132 | I/O — User I/O pin (group 1, bank 1) |
| ピン 133 | GND — Ground |
| ピン 134 | I/O — User I/O pin (group 1, bank 1) |
| ピン 135 | I/O — User I/O pin (group 1, bank 1) |
| ピン 136 | I/O — User I/O pin (group 1, bank 1) |
| ピン 137 | VCCIO — I/O supply voltage (3.3 V) |
| ピン 138 | I/O — User I/O pin (group 1, bank 1) |
| ピン 139 | I/O — User I/O pin (group 1, bank 1) |
| ピン 140 | I/O — User I/O pin (group 1, bank 1) |
| ピン 141 | GND — Ground |
| ピン 142 | I/O — User I/O pin (group 1, bank 1) |
| ピン 143 | I/O — User I/O pin (group 1, bank 1) |
| ピン 144 | I/O — User I/O pin (group 1, bank 1) |
主な用途
EPM3128ATI144-5N の用途: 6 件s: Industrial Control & Factory Automation Glue Logic, Telecommunications Backplane Bus Bridging, Consumer Electronics & Appliance Controllers, Legacy System Maintenance & 5 V-to-3.3 V Migration, PCI / Local Bus Interface Bridging, Test & Measurement Instrument Front-End Logic.
Industrial Control & Factory Automation Glue Logic
The EPM3128ATI144-5N fits industrial control applications because its 128 macrocells, 5.0 ns deterministic tPD, and -40C to +85C industrial temperature rating cover the full factory-floor envelope. It replaces discrete 74-series glue logic (address decoding, bus arbitration, handshaking) between microcontrollers, sensors, and motor drivers with a single 144-pin TQFP device. Its 96 user I/Os comfortably handle 16- to 32-bit data buses plus interrupt, control, and status lines. Unlike FPGAs, the MAX 3000A's EEPROM configuration boots in under 1 ms - critical for deterministic PLC startup sequencing. Used in PLCs, motor controllers, and field-bus gateways where instant-on, fixed timing, and ruggedized temperature range outweigh the need for high logic density.
おすすめ
Telecommunications Backplane Bus Bridging
The EPM3128ATI144-5N is widely used in telecom backplanes to bridge legacy buses (PCI, ISA, VME, H.110) to modern processors where its 192.3 MHz operation, 5.0 V input tolerance, and 96 I/Os are decisive advantages. It sits between the bus PHY and the switch ASIC, handling parity generation/checking, address decoding, and interrupt steering without external logic. The 5.0 V input tolerance allows direct connection to 5 V legacy devices, eliminating level translators - a 50% BOM savings over FPGA-based bridges that require 5 V-tolerant I/O standards. JTAG in-system programming allows field firmware updates via the backplane's JTAG chain.
おすすめ
Consumer Electronics & Appliance Controllers
In consumer electronics, the EPM3128ATI144-5N drives interface logic for washing machines, refrigerators, microwave ovens, and air-conditioner control boards. Its 3.3 V core, 5.0 V tolerant inputs, and small TQFP-144 footprint allow it to replace 3-5 discrete logic chips per board, cutting BOM cost and assembly time. Designers use the 96 I/Os to interface keypads, LED displays, sensor arrays, and relay drivers simultaneously. EEPROM-based instant-on eliminates the boot delay seen with FPGAs, so user button presses register on the first poll. Industrial temperature support lets the same BOM serve both indoor consumer and outdoor HVAC products.
おすすめ
Legacy System Maintenance & 5 V-to-3.3 V Migration
The EPM3128ATI144-5N is a drop-in modernization part for engineers migrating 5 V legacy boards to 3.3 V operation. Its 5.0 V tolerant inputs accept signals from 5 V devices directly, while the 3.3 V core connects to modern microcontrollers and ASICs - eliminating intermediate level shifters. The deterministic 5.0 ns tPD makes timing migration predictable: legacy timing budgets measured in 74-series gate delays translate directly. Industrial temperature support means field-deployed systems (medical, industrial control, instrumentation) can be retrofitted without re-qualification of the temperature envelope. JTAG boundary-scan supports both new validation and legacy test-pattern reuse.
おすすめ
PCI / Local Bus Interface Bridging
The EPM3128ATI144-5N frequently appears as a PCI bridge between an embedded CPU's local bus and the 33 MHz / 66 MHz PCI bus, leveraging its 5.0 ns tPD and 192.3 MHz fMAX to meet PCI's tight 7 ns setup/hold windows. It implements parity generation, bus arbitration (REQ/GNT), address decoding (IDSEL mapping), and interrupt steering (INTA/INTB/INTC/INTD) in a single device. The 96 user I/Os cover the full 32-bit PCI bus plus side-band signals, and the JTAG port allows field firmware updates to the bridge without removing the board. Industrial temperature support qualifies it for telecom and industrial-PCI applications alike.
おすすめ
Test & Measurement Instrument Front-End Logic
The EPM3128ATI144-5N is used in oscilloscopes, logic analyzers, and bench instruments as front-panel glue logic, multiplexing switch matrices, and trigger-conditioning circuits. Its deterministic 5.0 ns timing is ideal for high-speed trigger paths where FPGA routing variability is unacceptable. The 96 I/Os handle front-panel buttons, rotary encoders, status LEDs, and BNC trigger fan-out. JTAG allows bench engineers to load custom test patterns without removing the device. Industrial temperature rating and 3.3 V low-power operation suit portable, battery-powered instrument designs where EEPROM instant-on eliminates FPGA boot delays.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM3128ATI144-5N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM3128ATI144-10N | EPM3128ATC144-5N | EPM3128ATC144-10N | EPM3128ATC144-7N | EPM3128ATI144-10 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 (20x20 mm, 0.5 mm pitch) | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Speed Grade (tPD) | 5.0 ns (-5 grade) | 10 ns (-10 grade, slower) | 5.0 ns (-5 grade, same) | 10 ns (-10 grade, slower) | 7.5 ns (-7 grade) | 10 ns (-10 grade, slower) |
| Operating Temperature | -40C to +85C (industrial, I suffix) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Macro Cells | 128 | 128 (same) | 128 (same) | 128 (same) | 128 (same) | 128 (same) |
| Logic Gates | 2,500 | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) |
| User I/Os | 96 | 96 (same) | 96 (same) | 96 (same) | 96 (same) | 96 (same) |
| Maximum Frequency (fMAX) | 192.3 MHz | Lower (-10 grade, ~100 MHz) | 192.3 MHz (same) | Lower (-10 grade, ~100 MHz) | 148 MHz (-7 grade) | Lower (-10 grade, ~100 MHz) |
| Supply Voltage | 3.0 V to 3.6 V (3.3 V nominal) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) |
| Programming Interface | JTAG (IEEE 1149.1 BST) | JTAG (same) | JTAG (same) | JTAG (same) | JTAG (same) | JTAG (same) |
主な差別化要因
- Fastest speed grade in the MAX 3000A TQFP-144 family （vs EPM3128ATI144-10N)
- Industrial temperature range for harsh-environment deployments （vs EPM3128ATC144-5N)
- 5.0 V input tolerance for legacy bus interfacing （vs EPM1270T144C5N (MAX II))
設計ノート
The EPM3128ATI144-5N requires a single 3.3 V supply (3.0 V to 3.6 V) tied to both VCCINT and VCCIO. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCCINT and VCCIO pin (typically 16 caps total around the package periphery). Add a bulk 10 uF to 22 uF tantalum or ceramic capacitor near the device to suppress transient current spikes during simultaneous I/O switching. Estimated: at 192.3 MHz with 96 I/Os, peak transient current can reach 200-300 mA; ensure the regulator maintains regulation within 50 mV under this load step.
Route the four dedicated global clocks (GCLK1-GCLK4) on inner layers with ground reference and matched lengths within 0.5 inch to minimize pin-to-pin skew. According to MAX 3000A layout guidelines, the JTAG chain should be daisy-chained with TMS and TCK buffered once per chain to avoid signal integrity issues. Keep the TQFP-144 thermal/exposed pad (when present) soldered to a continuous ground pour with at least 9 thermal vias to the inner ground plane for improved theta_JA.
Do not exceed 5.0 V on any I/O pin even though the inputs are 5 V tolerant - the I/O pins do not tolerate voltages above 5.0 V absolute maximum. According to the MAX 3000A datasheet, leaving unused I/O pins floating can cause excess ICC; configure them as outputs driving low or as inputs with internal pull-ups enabled via the Quartus design software. For in-system programming, ensure the JTAG chain is terminated correctly with a pull-up on TCK/TMS/TDI and that no other devices hold the bus during programming.
コンプライアンス情報
RoHS and lead-free status not specified in verified web data; the N suffix historically indicates lead-free in Altera part numbering convention. AEC-Q100 not applicable - this is a commercial/industrial CPLD, not an automotive-qualified part.
