EPM3128ATI144-10N - 128-Macrocell MAX 3000A CPLD, 10ns | Intel / Altera
MPN: EPM3128ATI144-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $16.13 | $16.13 |
| 10 | $14.52 | $145.20 |
| 100 | $12.9 | $1,290.00 |
| 500 | $11.61 | $5,805.00 |
| 1,000 | $10.32 | $10,320.00 |
Drop-in alternatives for EPM3128ATI144-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM3128ATC144-10N
β Drop-Inβ In Stock
$6.56 / Unit
View Datasheet βEPM3128ATC144-10
β Drop-Inβ In Stock
$6.2 / Unit
View Datasheet βEPM3128ATC144-7N
β Drop-Inβ In Stock
$9.25 / Unit
View Datasheet βEPM3128ATI144-10AA
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM3128ATI144-10
β Drop-Inβ In Stock
$10.85 / Unit
View Datasheet βEPM7128AETC144-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM3128ATI144-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Logic Type | CMOS EEPROM-based CPLD |
| Macrocells | 128 |
| Typical Gates | 2.5K |
| User I/Os | 96 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Internal Frequency | 98 MHz |
| Supply Voltage (VCCINT) | 3.3 V |
| Output Bank Voltage (VCCIO) | 3.3 V or 2.5 V |
| Package | 144-pin TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | Industrial -40C to +85C |
| In-System Programmability | Yes (IEEE Std. 1532 compliant) |
| JTAG / Boundary Scan | Yes (IEEE 1149.1) |
| Configuration Memory | Non-volatile EEPROM |
| RoHS Status | Compliant |
EPM3128ATI144-10N Pin Configuration
| Pin 1 | I/O β User I/O (bank 1) |
| Pin 2 | I/O β User I/O (bank 1) |
| Pin 3 | I/O β User I/O (bank 1) |
| Pin 4 | I/O β User I/O (bank 1) |
| Pin 5 | I/O β User I/O (bank 1) |
| Pin 6 | I/O β User I/O (bank 1) |
| Pin 7 | I/O β User I/O (bank 1) |
| Pin 8 | I/O β User I/O (bank 1) |
| Pin 9 | VCCINT β 3.3 V core supply |
| Pin 10 | I/O β User I/O (bank 1) |
| Pin 11 | I/O β User I/O (bank 1) |
| Pin 12 | I/O β User I/O (bank 1) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O (bank 1) |
| Pin 15 | I/O β User I/O (bank 1) |
| Pin 16 | I/O β User I/O (bank 1) |
| Pin 17 | I/O β User I/O (bank 1) |
| Pin 18 | I/O β User I/O (bank 1) |
| Pin 19 | I/O β User I/O (bank 1) |
| Pin 20 | I/O β User I/O (bank 1) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O (bank 2) |
| Pin 23 | I/O β User I/O (bank 2) |
| Pin 24 | I/O β User I/O (bank 2) |
| Pin 25 | I/O β User I/O (bank 2) |
| Pin 26 | I/O β User I/O (bank 2) |
| Pin 27 | I/O β User I/O (bank 2) |
| Pin 28 | I/O β User I/O (bank 2) |
| Pin 29 | I/O β User I/O (bank 2) |
| Pin 30 | VCCIO1 β I/O bank 1 supply (3.3 V or 2.5 V) |
| Pin 31 | I/O β User I/O (bank 2) |
| Pin 32 | I/O β User I/O (bank 2) |
| Pin 33 | I/O β User I/O (bank 2) |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O (bank 2) |
| Pin 36 | I/O β User I/O (bank 2) |
| Pin 37 | I/O β User I/O (bank 2) |
| Pin 38 | I/O β User I/O (bank 2) |
| Pin 39 | I/O β User I/O (bank 2) |
| Pin 40 | I/O β User I/O (bank 2) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O (bank 2) |
| Pin 43 | I/O β User I/O (bank 2) |
| Pin 44 | I/O β User I/O (bank 2) |
| Pin 45 | I/O β User I/O (bank 2) |
| Pin 46 | I/O β User I/O (bank 2) |
| Pin 47 | I/O β User I/O (bank 2) |
| Pin 48 | I/O β User I/O (bank 2) |
| Pin 49 | I/O β User I/O (bank 2) |
| Pin 50 | VCCINT β 3.3 V core supply |
| Pin 51 | I/O β User I/O (bank 2) |
| Pin 52 | I/O β User I/O (bank 2) |
| Pin 53 | I/O β User I/O (bank 2) |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O (bank 2) |
| Pin 56 | I/O β User I/O (bank 2) |
| Pin 57 | I/O β User I/O (bank 2) |
| Pin 58 | I/O β User I/O (bank 2) |
| Pin 59 | I/O β User I/O (bank 2) |
| Pin 60 | I/O β User I/O (bank 2) |
| Pin 61 | GND β Ground |
| Pin 62 | TDI β JTAG test data in (IEEE 1149.1) |
| Pin 63 | TMS β JTAG test mode select |
| Pin 64 | TCK β JTAG test clock |
| Pin 65 | NC β Not connected (per datasheet) |
| Pin 66 | VCCIO2 β I/O bank 2 supply (3.3 V or 2.5 V) |
| Pin 67 | TDO β JTAG test data out |
| Pin 68 | I/O β User I/O (bank 3) |
| Pin 69 | I/O β User I/O (bank 3) |
| Pin 70 | I/O β User I/O (bank 3) |
| Pin 71 | I/O β User I/O (bank 3) |
| Pin 72 | I/O β User I/O (bank 3) |
| Pin 73 | GND β Ground |
| Pin 74 | I/O β User I/O (bank 3) |
| Pin 75 | I/O β User I/O (bank 3) |
| Pin 76 | I/O β User I/O (bank 3) |
| Pin 77 | I/O β User I/O (bank 3) |
| Pin 78 | I/O β User I/O (bank 3) |
| Pin 79 | I/O β User I/O (bank 3) |
| Pin 80 | I/O β User I/O (bank 3) |
| Pin 81 | VCCINT β 3.3 V core supply |
| Pin 82 | I/O β User I/O (bank 3) |
| Pin 83 | I/O β User I/O (bank 3) |
| Pin 84 | I/O β User I/O (bank 3) |
| Pin 85 | GND β Ground |
| Pin 86 | I/O β User I/O (bank 3) |
| Pin 87 | I/O β User I/O (bank 3) |
| Pin 88 | I/O β User I/O (bank 3) |
| Pin 89 | I/O β User I/O (bank 3) |
| Pin 90 | I/O β User I/O (bank 3) |
| Pin 91 | I/O β User I/O (bank 3) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O (bank 3) |
| Pin 94 | I/O β User I/O (bank 3) |
| Pin 95 | I/O β User I/O (bank 3) |
| Pin 96 | I/O β User I/O (bank 3) |
| Pin 97 | I/O β User I/O (bank 3) |
| Pin 98 | I/O β User I/O (bank 3) |
| Pin 99 | I/O β User I/O (bank 3) |
| Pin 100 | I/O β User I/O (bank 3) |
| Pin 101 | VCCINT β 3.3 V core supply |
| Pin 102 | I/O β User I/O (bank 4) |
| Pin 103 | I/O β User I/O (bank 4) |
| Pin 104 | I/O β User I/O (bank 4) |
| Pin 105 | I/O β User I/O (bank 4) |
| Pin 106 | I/O β User I/O (bank 4) |
| Pin 107 | I/O β User I/O (bank 4) |
| Pin 108 | I/O β User I/O (bank 4) |
| Pin 109 | I/O β User I/O (bank 4) |
| Pin 110 | VCCIO3 β I/O bank 3 supply (3.3 V or 2.5 V) |
| Pin 111 | I/O β User I/O (bank 4) |
| Pin 112 | I/O β User I/O (bank 4) |
| Pin 113 | I/O β User I/O (bank 4) |
| Pin 114 | GND β Ground |
| Pin 115 | I/O β User I/O (bank 4) |
| Pin 116 | I/O β User I/O (bank 4) |
| Pin 117 | I/O β User I/O (bank 4) |
| Pin 118 | I/O β User I/O (bank 4) |
| Pin 119 | I/O β User I/O (bank 4) |
| Pin 120 | I/O β User I/O (bank 4) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O (bank 4) |
| Pin 123 | I/O β User I/O (bank 4) |
| Pin 124 | I/O β User I/O (bank 4) |
| Pin 125 | I/O β User I/O (bank 4) |
| Pin 126 | I/O β User I/O (bank 4) |
| Pin 127 | I/O β User I/O (bank 4) |
| Pin 128 | I/O β User I/O (bank 4) |
| Pin 129 | I/O β User I/O (bank 4) |
| Pin 130 | VCCINT β 3.3 V core supply |
| Pin 131 | I/O β User I/O (bank 4) |
| Pin 132 | I/O β User I/O (bank 4) |
| Pin 133 | I/O β User I/O (bank 4) |
| Pin 134 | GND β Ground |
| Pin 135 | OE2 β Output enable 2 / global control |
| Pin 136 | OE1 β Output enable 1 / global control |
| Pin 137 | GND β Ground |
| Pin 138 | CLK2 β Global clock input 2 |
| Pin 139 | CLK1 β Global clock input 1 |
| Pin 140 | VCCIO4 β I/O bank 4 supply (3.3 V or 2.5 V) |
| Pin 141 | INPUT/GCLK1 β Input / global clear |
| Pin 142 | MSEL1 β Mode select 1 (ISP configuration) |
| Pin 143 | MSEL0 β Mode select 0 (ISP configuration) |
| Pin 144 | CONF_DONE β Configuration done (open-drain) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATI144-10N is suitable for 6 applications: Microcontroller Bus Glue Logic, Power-Supply Sequencing & Supervisory Control, Address Decoding & Chip-Select Generation, I/O Expansion & Level Translation, Industrial State Machines & Sequencers, Legacy Logic Replacement (74-Series Substitution).
Microcontroller Bus Glue Logic
The EPM3128ATI144-10N's 128 macrocells and 96 user I/Os make it ideal for microcontroller bus glue logic where address decoding, chip-select generation, and wait-state insertion must be implemented in deterministic, non-volatile hardware. Placed between an MCU and peripheral memories or ASICs, the CPLD replaces dozens of 74-series logic packages with a single device. The 10 ns tPD adds less than one 50 MHz bus cycle of latency, which is invisible to most MCU reads. Instant-on EEPROM configuration eliminates the boot-PROM overhead typical of SRAM-based FPGAs.
Recommended
Power-Supply Sequencing & Supervisory Control
The EPM3128ATI144-10N is well suited to multi-rail power-supply sequencing controllers in industrial and communications equipment. Its 96 I/Os can drive PG (power-good) and EN lines for many voltage rails, while state-machine logic implemented in macrocells enforces turn-on and turn-off ordering. The non-volatile EEPROM configuration means sequencing starts correctly on every power cycle without boot latency. 3.3 V VCCINT and selectable 3.3 V / 2.5 V VCCIO allow direct interface to most modern point-of-load regulators.
Recommended
Address Decoding & Chip-Select Generation
The MAX 3000A's wide AND-OR product-term macrocells excel at address decoding, where many input pins (often 16-24 address bits) must be combined to generate a single chip-select output. The EPM3128ATI144-10N's 96 user I/Os comfortably accept a 24-bit address bus plus several qualifier lines (read/write, chip-enable, burst) and produce up to 96 chip-select outputs - more than enough for full memory and I/O decoding on embedded processor platforms. The 10 ns tPD keeps decode latency below one clock cycle at typical 33-50 MHz bus speeds.
Recommended
I/O Expansion & Level Translation
With selectable 3.3 V / 2.5 V VCCIO banks, the EPM3128ATI144-10N is a natural voltage-level translator between mixed-voltage domains on a single board. It can be configured to translate parallel buses between a 3.3 V FPGA and 2.5 V memory or peripheral ASICs without dedicated level-shifter ICs. The 96 user I/Os support wide data buses and the macrocell registers double as small FIFO / handshake buffers when both clock domains are crossed in the same device.
Recommended
Industrial State Machines & Sequencers
The industrial -40C to +85C operating temperature range of the EPM3128ATI144-10N makes it suitable for factory-floor controllers, motor-control sequencers, and other industrial applications. The 128 macrocells can host multiple parallel Moore or Mealy state machines for stepper-motor commutation, conveyor indexing, or safety-interlock logic. Non-volatile EEPROM configuration means the controller resumes its state machine exactly where it left off after power cycles - critical for unattended industrial equipment.
Recommended
Legacy Logic Replacement (74-Series Substitution)
A single EPM3128ATI144-10N can replace an entire board of 74HC/74AHC glue logic - address latches, bus transceivers, parity generators, interrupt controllers, and shift registers. This consolidation reduces PCB area, improves reliability by eliminating inter-chip wiring, and adds reconfigurability for late design changes. The IEEE Std. 1532-compliant ISP allows the replacement device to be re-programmed on the production line without removing it from the board, accelerating ECO cycles and reducing inventory of legacy logic SKUs.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATI144-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATC144-10N | EPM3128ATC144-10 | EPM3128ATC144-7N | EPM3128ATI144-10AA | EPM3128ATI144-10 | EPM7128AETC144-10N |
|---|---|---|---|---|---|---|---|
| Package | 144-pin TQFP | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same | 144-pin TQFP - same |
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel | Intel |
| Family | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 3000A | MAX 7000AE |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 96 | 96 | 96 | 96 | 96 | 96 | 100 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7 ns (-30%, faster) | 10 ns | 10 ns | 10 ns |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) |
| Lead-Free Finish | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | Yes (Pb-free) | No (legacy) | Yes (Pb-free) |
Key Differentiators
- Industrial temperature grade vs commercial-temperature same-die variant (vs EPM3128ATC144-10N)
- Pb-free RoHS-compliant lead finish (vs EPM3128ATI144-10 (no -N suffix))
- 10 ns tPD provides 30% timing margin over legacy 74HC logic (vs Discrete 74HC / 74AHC glue logic)
- Same TQFP-144 footprint, faster speed-grade upgrade available (vs EPM3128ATC144-7N)
Design Notes
The 144-pin TQFP package has 0.5 mm lead pitch, which demands a 4-layer PCB with a continuous ground plane under the device to control impedance and crosstalk on the 96 user I/Os. Place a 0.1 uF X7R decoupling capacitor within 5 mm of every VCCINT pin and every VCCIO bank pin, plus a single 10 uF bulk tantalum or ceramic capacitor per VCCIO bank. Avoid routing signal traces beneath the package body or the exposed die-pad region. The recommended land pattern and thermal land are shown in the MAX 3000A device handbook.
Although the MAX 3000A family uses a non-volatile EEPROM configuration with predictable, fixed routing delays, the 96 high-frequency I/Os at 98 MHz can still generate simultaneous-switching noise (SSN). Reserve one GND pin adjacent to each switching output bank and add a ferrite bead on the VCCIO supply if the bank drives long traces (>50 mm) or >8 simultaneous outputs. JTAG signals TCK and TMS should be guarded with ground traces on both sides for noise immunity.
Do not mix VCCIO bank voltages beyond the supported 3.3 V or 2.5 V options - 1.8 V peripherals require an external level shifter. The CONF_DONE pin is open-drain and requires an external 10 kohm pull-up to VCCIO. Setting OE1/OE2 incorrectly will tristate entire I/O banks and masquerade as a 'dead' board. When using ISP through the JTAG pins, ensure that TMS and TDI are not held low at power-up to prevent unintended entry into JTAG states.
The MAX 3000A family has very low static power consumption (typical Icc < 50 mA at 3.3 V) because the EEPROM configuration has no DC refresh current. However, dynamic power scales with toggle frequency and output loading. At 96 I/Os toggling at 98 MHz into 30 pF loads each, total dynamic power can reach ~500 mW. Provide a copper pour area of at least 1 square inch on the top layer connected to the exposed thermal pad (TQFP variant) to keep junction temperature below 125 C at industrial ambient.
Compliance Information
Pb-free matte-tin lead finish per JEDEC J-STD-609. Industrial temperature grade -40C to +85C. Not AEC-Q100 qualified (industrial, not automotive).
