EPM3128ATI144-5N - 128-Macrocell 2.5K CPLD MAX 3000A | Altera
MPN: EPM3128ATI144-5N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.4 | $164.00 |
| 100 | $14.2 | $1,420.00 |
| 500 | $12.1 | $6,050.00 |
| 1,000 | $10.5 | $10,500.00 |
Drop-in alternatives for EPM3128ATI144-5N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM3128ATI144-10N
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View Datasheet →EPM3128ATC144-5N
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View Datasheet →EPM3128ATI144-10
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View Datasheet →EPM3128ATI144-5N Maximum Ratings & Electrical Characteristics
| Family | MAX 3000A |
| Logic Gates | 2,500 gates |
| Macro Cells | 128 |
| User I/Os | 96 |
| Maximum Operating Frequency | 192.3 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 5.0 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| I/O Standard | LVCMOS / LVTTL (5.0 V tolerant inputs) |
| Programming Interface | JTAG (IEEE 1149.1 BST) - in-system |
| Process Technology | 0.30 um CMOS EEPROM |
| Configuration Memory | Non-volatile on-chip EEPROM |
| Package | TQFP-144 (20x20 mm, 0.5 mm pitch) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) |
| MSL Level | 3 (168 hours) |
EPM3128ATI144-5N Pin Configuration
| Pin 1 | I/O — User I/O pin (group 1, bank 1) |
| Pin 2 | I/O — User I/O pin (group 1, bank 1) |
| Pin 3 | I/O — User I/O pin (group 1, bank 1) |
| Pin 4 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 5 | I/O — User I/O pin (group 1, bank 1) |
| Pin 6 | I/O — User I/O pin (group 1, bank 1) |
| Pin 7 | I/O — User I/O pin (group 1, bank 1) |
| Pin 8 | GND — Ground |
| Pin 9 | I/O — User I/O pin (group 1, bank 2) |
| Pin 10 | I/O — User I/O pin (group 1, bank 2) |
| Pin 11 | I/O — User I/O pin (group 1, bank 2) |
| Pin 12 | VCCINT — Core supply voltage (3.3 V) |
| Pin 13 | I/O — User I/O pin (group 1, bank 2) |
| Pin 14 | I/O — User I/O pin (group 1, bank 2) |
| Pin 15 | I/O — User I/O pin (group 1, bank 2) |
| Pin 16 | GND — Ground |
| Pin 17 | I/O — User I/O pin (group 1, bank 2) |
| Pin 18 | I/O — User I/O pin (group 1, bank 2) |
| Pin 19 | I/O — User I/O pin (group 1, bank 2) |
| Pin 20 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 21 | I/O — User I/O pin (group 1, bank 2) |
| Pin 22 | I/O — User I/O pin (group 1, bank 2) |
| Pin 23 | I/O — User I/O pin (group 1, bank 2) |
| Pin 24 | GND — Ground |
| Pin 25 | I/O — User I/O pin (group 1, bank 2) |
| Pin 26 | I/O — User I/O pin (group 1, bank 2) |
| Pin 27 | I/O — User I/O pin (group 1, bank 2) |
| Pin 28 | INPUT/GCLK1 — Dedicated input / global clock 1 |
| Pin 29 | INPUT/GCLK3 — Dedicated input / global clock 3 |
| Pin 30 | I/O — User I/O pin (group 2, bank 3) |
| Pin 31 | I/O — User I/O pin (group 2, bank 3) |
| Pin 32 | I/O — User I/O pin (group 2, bank 3) |
| Pin 33 | GND — Ground |
| Pin 34 | I/O — User I/O pin (group 2, bank 3) |
| Pin 35 | I/O — User I/O pin (group 2, bank 3) |
| Pin 36 | I/O — User I/O pin (group 2, bank 3) |
| Pin 37 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 38 | I/O — User I/O pin (group 2, bank 3) |
| Pin 39 | I/O — User I/O pin (group 2, bank 3) |
| Pin 40 | I/O — User I/O pin (group 2, bank 3) |
| Pin 41 | GND — Ground |
| Pin 42 | I/O — User I/O pin (group 2, bank 3) |
| Pin 43 | I/O — User I/O pin (group 2, bank 3) |
| Pin 44 | I/O — User I/O pin (group 2, bank 3) |
| Pin 45 | VCCINT — Core supply voltage (3.3 V) |
| Pin 46 | I/O — User I/O pin (group 2, bank 3) |
| Pin 47 | I/O — User I/O pin (group 2, bank 3) |
| Pin 48 | I/O — User I/O pin (group 2, bank 3) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O pin (group 2, bank 3) |
| Pin 51 | I/O — User I/O pin (group 2, bank 3) |
| Pin 52 | I/O — User I/O pin (group 2, bank 3) |
| Pin 53 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 54 | I/O — User I/O pin (group 2, bank 3) |
| Pin 55 | I/O — User I/O pin (group 2, bank 3) |
| Pin 56 | I/O — User I/O pin (group 2, bank 3) |
| Pin 57 | GND — Ground |
| Pin 58 | I/O — User I/O pin (group 2, bank 3) |
| Pin 59 | I/O — User I/O pin (group 2, bank 3) |
| Pin 60 | I/O — User I/O pin (group 2, bank 3) |
| Pin 61 | INPUT/GCLK2 — Dedicated input / global clock 2 |
| Pin 62 | INPUT/GCLK4 — Dedicated input / global clock 4 |
| Pin 63 | I/O — User I/O pin (group 3, bank 4) |
| Pin 64 | I/O — User I/O pin (group 3, bank 4) |
| Pin 65 | I/O — User I/O pin (group 3, bank 4) |
| Pin 66 | GND — Ground |
| Pin 67 | I/O — User I/O pin (group 3, bank 4) |
| Pin 68 | I/O — User I/O pin (group 3, bank 4) |
| Pin 69 | I/O — User I/O pin (group 3, bank 4) |
| Pin 70 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 71 | I/O — User I/O pin (group 3, bank 4) |
| Pin 72 | I/O — User I/O pin (group 3, bank 4) |
| Pin 73 | I/O — User I/O pin (group 3, bank 4) |
| Pin 74 | GND — Ground |
| Pin 75 | I/O — User I/O pin (group 3, bank 4) |
| Pin 76 | I/O — User I/O pin (group 3, bank 4) |
| Pin 77 | I/O — User I/O pin (group 3, bank 4) |
| Pin 78 | VCCINT — Core supply voltage (3.3 V) |
| Pin 79 | I/O — User I/O pin (group 3, bank 4) |
| Pin 80 | I/O — User I/O pin (group 3, bank 4) |
| Pin 81 | I/O — User I/O pin (group 3, bank 4) |
| Pin 82 | GND — Ground |
| Pin 83 | I/O — User I/O pin (group 3, bank 4) |
| Pin 84 | I/O — User I/O pin (group 3, bank 4) |
| Pin 85 | I/O — User I/O pin (group 3, bank 4) |
| Pin 86 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 87 | I/O — User I/O pin (group 3, bank 4) |
| Pin 88 | I/O — User I/O pin (group 3, bank 4) |
| Pin 89 | I/O — User I/O pin (group 3, bank 4) |
| Pin 90 | GND — Ground |
| Pin 91 | I/O — User I/O pin (group 3, bank 4) |
| Pin 92 | I/O — User I/O pin (group 3, bank 4) |
| Pin 93 | I/O — User I/O pin (group 3, bank 4) |
| Pin 94 | TDI — JTAG test data input |
| Pin 95 | TMS — JTAG test mode select |
| Pin 96 | TCK — JTAG test clock |
| Pin 97 | NC — Not connected (per datasheet) |
| Pin 98 | NC — Not connected (per datasheet) |
| Pin 99 | NC — Not connected (per datasheet) |
| Pin 100 | TDO — JTAG test data output |
| Pin 101 | I/O — User I/O pin (group 4, bank 1) |
| Pin 102 | I/O — User I/O pin (group 4, bank 1) |
| Pin 103 | I/O — User I/O pin (group 4, bank 1) |
| Pin 104 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 105 | I/O — User I/O pin (group 4, bank 1) |
| Pin 106 | I/O — User I/O pin (group 4, bank 1) |
| Pin 107 | I/O — User I/O pin (group 4, bank 1) |
| Pin 108 | GND — Ground |
| Pin 109 | I/O — User I/O pin (group 4, bank 1) |
| Pin 110 | I/O — User I/O pin (group 4, bank 1) |
| Pin 111 | I/O — User I/O pin (group 4, bank 1) |
| Pin 112 | VCCINT — Core supply voltage (3.3 V) |
| Pin 113 | I/O — User I/O pin (group 4, bank 1) |
| Pin 114 | I/O — User I/O pin (group 4, bank 1) |
| Pin 115 | I/O — User I/O pin (group 4, bank 1) |
| Pin 116 | GND — Ground |
| Pin 117 | I/O — User I/O pin (group 4, bank 1) |
| Pin 118 | I/O — User I/O pin (group 4, bank 1) |
| Pin 119 | I/O — User I/O pin (group 4, bank 1) |
| Pin 120 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 121 | I/O — User I/O pin (group 4, bank 1) |
| Pin 122 | I/O — User I/O pin (group 4, bank 1) |
| Pin 123 | I/O — User I/O pin (group 4, bank 1) |
| Pin 124 | GND — Ground |
| Pin 125 | I/O — User I/O pin (group 4, bank 1) |
| Pin 126 | I/O — User I/O pin (group 4, bank 1) |
| Pin 127 | I/O — User I/O pin (group 4, bank 1) |
| Pin 128 | INPUT/OE — Dedicated input / output enable |
| Pin 129 | INPUT/CLR — Dedicated input / clear |
| Pin 130 | I/O — User I/O pin (group 1, bank 1) |
| Pin 131 | I/O — User I/O pin (group 1, bank 1) |
| Pin 132 | I/O — User I/O pin (group 1, bank 1) |
| Pin 133 | GND — Ground |
| Pin 134 | I/O — User I/O pin (group 1, bank 1) |
| Pin 135 | I/O — User I/O pin (group 1, bank 1) |
| Pin 136 | I/O — User I/O pin (group 1, bank 1) |
| Pin 137 | VCCIO — I/O supply voltage (3.3 V) |
| Pin 138 | I/O — User I/O pin (group 1, bank 1) |
| Pin 139 | I/O — User I/O pin (group 1, bank 1) |
| Pin 140 | I/O — User I/O pin (group 1, bank 1) |
| Pin 141 | GND — Ground |
| Pin 142 | I/O — User I/O pin (group 1, bank 1) |
| Pin 143 | I/O — User I/O pin (group 1, bank 1) |
| Pin 144 | I/O — User I/O pin (group 1, bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM3128ATI144-5N is suitable for 6 applications: Industrial Control & Factory Automation Glue Logic, Telecommunications Backplane Bus Bridging, Consumer Electronics & Appliance Controllers, Legacy System Maintenance & 5 V-to-3.3 V Migration, PCI / Local Bus Interface Bridging, Test & Measurement Instrument Front-End Logic.
Industrial Control & Factory Automation Glue Logic
The EPM3128ATI144-5N fits industrial control applications because its 128 macrocells, 5.0 ns deterministic tPD, and -40C to +85C industrial temperature rating cover the full factory-floor envelope. It replaces discrete 74-series glue logic (address decoding, bus arbitration, handshaking) between microcontrollers, sensors, and motor drivers with a single 144-pin TQFP device. Its 96 user I/Os comfortably handle 16- to 32-bit data buses plus interrupt, control, and status lines. Unlike FPGAs, the MAX 3000A's EEPROM configuration boots in under 1 ms - critical for deterministic PLC startup sequencing. Used in PLCs, motor controllers, and field-bus gateways where instant-on, fixed timing, and ruggedized temperature range outweigh the need for high logic density.
Recommended
Telecommunications Backplane Bus Bridging
The EPM3128ATI144-5N is widely used in telecom backplanes to bridge legacy buses (PCI, ISA, VME, H.110) to modern processors where its 192.3 MHz operation, 5.0 V input tolerance, and 96 I/Os are decisive advantages. It sits between the bus PHY and the switch ASIC, handling parity generation/checking, address decoding, and interrupt steering without external logic. The 5.0 V input tolerance allows direct connection to 5 V legacy devices, eliminating level translators - a 50% BOM savings over FPGA-based bridges that require 5 V-tolerant I/O standards. JTAG in-system programming allows field firmware updates via the backplane's JTAG chain.
Recommended
Consumer Electronics & Appliance Controllers
In consumer electronics, the EPM3128ATI144-5N drives interface logic for washing machines, refrigerators, microwave ovens, and air-conditioner control boards. Its 3.3 V core, 5.0 V tolerant inputs, and small TQFP-144 footprint allow it to replace 3-5 discrete logic chips per board, cutting BOM cost and assembly time. Designers use the 96 I/Os to interface keypads, LED displays, sensor arrays, and relay drivers simultaneously. EEPROM-based instant-on eliminates the boot delay seen with FPGAs, so user button presses register on the first poll. Industrial temperature support lets the same BOM serve both indoor consumer and outdoor HVAC products.
Recommended
Legacy System Maintenance & 5 V-to-3.3 V Migration
The EPM3128ATI144-5N is a drop-in modernization part for engineers migrating 5 V legacy boards to 3.3 V operation. Its 5.0 V tolerant inputs accept signals from 5 V devices directly, while the 3.3 V core connects to modern microcontrollers and ASICs - eliminating intermediate level shifters. The deterministic 5.0 ns tPD makes timing migration predictable: legacy timing budgets measured in 74-series gate delays translate directly. Industrial temperature support means field-deployed systems (medical, industrial control, instrumentation) can be retrofitted without re-qualification of the temperature envelope. JTAG boundary-scan supports both new validation and legacy test-pattern reuse.
Recommended
PCI / Local Bus Interface Bridging
The EPM3128ATI144-5N frequently appears as a PCI bridge between an embedded CPU's local bus and the 33 MHz / 66 MHz PCI bus, leveraging its 5.0 ns tPD and 192.3 MHz fMAX to meet PCI's tight 7 ns setup/hold windows. It implements parity generation, bus arbitration (REQ/GNT), address decoding (IDSEL mapping), and interrupt steering (INTA/INTB/INTC/INTD) in a single device. The 96 user I/Os cover the full 32-bit PCI bus plus side-band signals, and the JTAG port allows field firmware updates to the bridge without removing the board. Industrial temperature support qualifies it for telecom and industrial-PCI applications alike.
Recommended
Test & Measurement Instrument Front-End Logic
The EPM3128ATI144-5N is used in oscilloscopes, logic analyzers, and bench instruments as front-panel glue logic, multiplexing switch matrices, and trigger-conditioning circuits. Its deterministic 5.0 ns timing is ideal for high-speed trigger paths where FPGA routing variability is unacceptable. The 96 I/Os handle front-panel buttons, rotary encoders, status LEDs, and BNC trigger fan-out. JTAG allows bench engineers to load custom test patterns without removing the device. Industrial temperature rating and 3.3 V low-power operation suit portable, battery-powered instrument designs where EEPROM instant-on eliminates FPGA boot delays.
Recommended
Recommended Products Summary
Engineering reference data for EPM3128ATI144-5N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM3128ATI144-10N | EPM3128ATC144-5N | EPM3128ATC144-10N | EPM3128ATC144-7N | EPM3128ATI144-10 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 (20x20 mm, 0.5 mm pitch) | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same | TQFP-144 - same |
| Brand | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) | Altera (Intel PSG) |
| Speed Grade (tPD) | 5.0 ns (-5 grade) | 10 ns (-10 grade, slower) | 5.0 ns (-5 grade, same) | 10 ns (-10 grade, slower) | 7.5 ns (-7 grade) | 10 ns (-10 grade, slower) |
| Operating Temperature | -40C to +85C (industrial, I suffix) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Macro Cells | 128 | 128 (same) | 128 (same) | 128 (same) | 128 (same) | 128 (same) |
| Logic Gates | 2,500 | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) | 2,500 (same) |
| User I/Os | 96 | 96 (same) | 96 (same) | 96 (same) | 96 (same) | 96 (same) |
| Maximum Frequency (fMAX) | 192.3 MHz | Lower (-10 grade, ~100 MHz) | 192.3 MHz (same) | Lower (-10 grade, ~100 MHz) | 148 MHz (-7 grade) | Lower (-10 grade, ~100 MHz) |
| Supply Voltage | 3.0 V to 3.6 V (3.3 V nominal) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) | 3.0 V to 3.6 V (same) |
| Programming Interface | JTAG (IEEE 1149.1 BST) | JTAG (same) | JTAG (same) | JTAG (same) | JTAG (same) | JTAG (same) |
Key Differentiators
- Fastest speed grade in the MAX 3000A TQFP-144 family (vs EPM3128ATI144-10N)
- Industrial temperature range for harsh-environment deployments (vs EPM3128ATC144-5N)
- 5.0 V input tolerance for legacy bus interfacing (vs EPM1270T144C5N (MAX II))
Design Notes
The EPM3128ATI144-5N requires a single 3.3 V supply (3.0 V to 3.6 V) tied to both VCCINT and VCCIO. Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCCINT and VCCIO pin (typically 16 caps total around the package periphery). Add a bulk 10 uF to 22 uF tantalum or ceramic capacitor near the device to suppress transient current spikes during simultaneous I/O switching. Estimated: at 192.3 MHz with 96 I/Os, peak transient current can reach 200-300 mA; ensure the regulator maintains regulation within 50 mV under this load step.
Route the four dedicated global clocks (GCLK1-GCLK4) on inner layers with ground reference and matched lengths within 0.5 inch to minimize pin-to-pin skew. According to MAX 3000A layout guidelines, the JTAG chain should be daisy-chained with TMS and TCK buffered once per chain to avoid signal integrity issues. Keep the TQFP-144 thermal/exposed pad (when present) soldered to a continuous ground pour with at least 9 thermal vias to the inner ground plane for improved theta_JA.
Do not exceed 5.0 V on any I/O pin even though the inputs are 5 V tolerant - the I/O pins do not tolerate voltages above 5.0 V absolute maximum. According to the MAX 3000A datasheet, leaving unused I/O pins floating can cause excess ICC; configure them as outputs driving low or as inputs with internal pull-ups enabled via the Quartus design software. For in-system programming, ensure the JTAG chain is terminated correctly with a pull-up on TCK/TMS/TDI and that no other devices hold the bus during programming.
Compliance Information
RoHS and lead-free status not specified in verified web data; the N suffix historically indicates lead-free in Altera part numbering convention. AEC-Q100 not applicable - this is a commercial/industrial CPLD, not an automotive-qualified part.
