EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
部品番号: EPM5192AJC84-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.4 | $2,640.00 |
| 500 | $21.95 | $10,975.00 |
| 1,000 | $19.2 | $19,200.00 |
EPM5192AJC84-20 概要
What is a UV-erasable CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on digital IC that implements glue logic, bus arbitration, state machines, and address decoding in a single chip. The UV-erasable (windowed) variant adds a quartz window above the die that lets an external UV lamp reset the on-chip EEPROM-like switches, so the same physical package can be re-programmed many times during prototyping. Within the broader taxonomy, a CPLD belongs to programmable logic devices (PLD), which themselves sit under digital logic ICs and semiconductor devices.
Key features include 192 macrocells arranged in Logic Array Blocks (LABs), a programmable interconnect switch matrix, 64 bidirectional I/O pins, 7 dedicated clock/input pins, and a 33 ns pin-to-pin delay (the “-20” speed grade). The device is built on a CMOS EEPROM technology that delivers deterministic propagation delay regardless of logic utilization, which is critical for synchronous designs.
Architecturally, the EPM5192 integrates the AND/OR array with output macrocells that contain programmable flip-flops, making it well suited for both combinatorial and registered designs. The UV window enables up to thousands of erase/reprogram cycles during development, although the part is one-time-programmable once the window label is removed for production.
Typical applications include glue logic for legacy 5 V microprocessor and DSP systems, bus-interface and address-decoding logic, peripheral controllers in industrial control, and replacement of multiple 74-series TTL/CMOS gates in compact boards. Designers of long-life industrial and military systems also rely on this part for its deterministic timing and field-proven reliability.
Designers should plan a 10–15 percent I/O and macrocell margin, use Altera MAX+PLUS II or Quartus for design entry, and budget for the UV-erase cycle (~30 minutes under a 12,000 uW/cm² lamp) if iterative prototyping is required. The 84-pin J-lead PLCC accepts standard socket or surface-mount footprints, easing both production and rework.
ドロップイン代替品: EPM5192AJC84-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM5192AJC84-20 （同一形状・フットプリント） — 相違点: Package, Device Type, Mounting Type, Process Technology, Supply Voltage (VCC).
クイック比較ツール — 並列比較する代替部品を選択:
EPM5192AJC84-15
✅ ドロップイン✓ 在庫あり
$18.95 / 個
データシートを見る →EPM5192AGC84-20
✅ ドロップイン✓ 在庫あり
$41.2 / 個
データシートを見る →EPM5192AGC84-15
✅ ドロップイン✓ 在庫あり
$42 / 個
データシートを見る →EPM5192AJC-25
✅ ドロップイン✓ 在庫あり
$8.2 / 個
データシートを見る →EPM5192AJC-15
✅ ドロップイン✓ 在庫あり
$9.85 / 個
データシートを見る →ATF1508ASL-25JI84
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM5192AJC84-20 最大定格＆電気的特性
| Family | MAX 5000 |
| Device Type | UV-erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 |
| Propagation Delay (tpd) | 33 ns (speed grade -20) |
| 最大クロック周波数 | 66.7 MHz |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V |
| Dedicated Inputs | 7 |
| User I/O Lines | 64 |
| Process Technology | CMOS, UV-erasable EEPROM |
| パッケージ | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Operating Temperature Grade | Commercial |
| 実装タイプ | Surface Mount (J-Lead) |
| Programming Tool | Altera MAX+PLUS II / Quartus (legacy) |
EPM5192AJC84-20 ピン構成
| ピン 1 | I/O — User I/O pin (bidirectional) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | GND — Ground |
| ピン 15 | I/O — User I/O pin |
| ピン 16 | I/O — User I/O pin |
| ピン 17 | I/O — User I/O pin |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | INPUT — Dedicated input pin |
| ピン 22 | INPUT — Dedicated input pin (clock) |
| ピン 23 | INPUT — Dedicated input pin |
| ピン 24 | INPUT — Dedicated input pin |
| ピン 25 | INPUT — Dedicated input pin (OE) |
| ピン 26 | INPUT — Dedicated input pin |
| ピン 27 | INPUT — Dedicated input pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | I/O — User I/O pin |
| ピン 42 | VCC — 5 V supply |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | VCC — 5 V supply |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | GND — Ground |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | I/O — User I/O pin |
主な用途
EPM5192AJC84-20 の用途: 6 件s: Legacy 5 V Microprocessor Glue Logic, Industrial Control State Machines, Peripheral and Bus Interface Controllers, Replacement of Multiple 74-Series TTL Gates, Long-Life Military and Aerospace Systems, Test and Measurement Instrument Front Ends.
Legacy 5 V Microprocessor Glue Logic
The EPM5192AJC84-20 fits legacy 5 V Intel 80x86, 68k, and DSP glue-logic designs where 192 macrocells, 64 user I/O, and 33 ns deterministic pin-to-pin delay are required to implement address decoding, wait-state generation, and bus arbitration. Its single 5 V supply, 5 V-tolerant CMOS I/O, and instant-on non-volatile configuration eliminate the boot PROM and simplify board bring-up. The 84-pin PLCC J-Lead package accepts sockets for fast field upgrades, while the UV window allows hundreds of design iterations during bring-up. Designers retain MAX+PLUS II compatibility for legacy toolchain reuse.
おすすめ
Industrial Control State Machines
The EPM5192AJC84-20 is well suited to industrial PLCs and motor-control boards that demand deterministic timing and 5 V tolerance in electrically noisy factory environments. The 192 macrocells comfortably hold large Moore/Mealy state machines for sequencing, while the 33 ns tpd supports 66.7 MHz control loops. Its non-volatile EEPROM configuration retains state through brown-out events, eliminating external watchdogs in many designs. The commercial temperature grade and PLCC package ease conformal-coat rework during long-life field service, and the device is widely available on the surplus channel.
おすすめ
Peripheral and Bus Interface Controllers
The EPM5192AJC84-20 implements peripheral controllers for ISA, VME, and parallel-bus interfaces in long-lifecycle embedded systems. Its 64 user I/O directly drive 8/16-bit data plus full address/control buses, while the 7 dedicated inputs accept clock and strobe signals. Deterministic 33 ns propagation delay simplifies worst-case bus-turnaround analysis, and the non-volatile configuration eliminates external boot PROMs. The PLCC J-Lead package accepts standard through-hole sockets for prototype bring-up and surface-mount soldering for volume production.
おすすめ
Replacement of Multiple 74-Series TTL Gates
Designers consolidating dozens of 74LS/74HC/74FTTL chips onto a single non-volatile device use the EPM5192AJC84-20 to reduce board area, power, and inventory SKUs. The 192 macrocells and 64 user I/O are typically more than enough to absorb the equivalent of 30–50 SSI/MSI gates plus registered logic, while the 33 ns tpd matches the slowest 74LS part. Power consumption drops because the CPLD only toggles the logic actually used, and the PLCC package supports both socketed prototyping and SMD production.
おすすめ
Long-Life Military and Aerospace Systems
The EPM5192AJC84-20 and its military-grade sibling EPM5192AGC84-20 serve long-life avionics, naval, and ground-vehicle systems where re-qualification cycles preclude modernization. The MAX 5000 architecture is field-proven over decades, and the Altera/Intel FPGA legacy program continues to support key customers. The 192 macrocells handle multi-channel MIL-STD-1553 / ARINC 429 glue logic and timing, while the PLCC package with J-leads withstands the mechanical shock and vibration of military environments. The UV window supports field re-programming during depot-level maintenance.
おすすめ
Test and Measurement Instrument Front Ends
The EPM5192AJC84-20 fits legacy test instruments and bench-top measurement gear where deterministic timing and 5 V tolerance simplify front-end design. The 192 macrocells implement encoder/decoder logic, range-switching sequencers, and front-panel multiplexer control, while 64 I/O drive displays and parallel ADCs. Its 33 ns tpd supports 25–30 MHz sample-rate handshaking, and the non-volatile configuration eliminates boot PROMs. The 84-pin PLCC package accepts sockets for calibration updates, and the device is widely supported on the surplus channel for cost-sensitive instrument production.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM5192AJC84-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM5192AJC84-15 | EPM5192AGC84-20 | EPM5192AGC84-15 | EPM5192AJC-25 | EPM5192AJC-15 | ATF1508ASL-25JI84 |
|---|---|---|---|---|---|---|---|
| Package | 84-pin PLCC J-Lead (WQCCJ) | 84-pin PLCC J-Lead - same | 84-pin PLCC J-Lead - same | 84-pin PLCC J-Lead - same | 84-pin PLCC J-Lead - same | 84-pin PLCC J-Lead - same | 84-pin PLCC J-Lead - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Microchip Technology |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 | 128 |
| Propagation Delay (tpd) | 33 ns | 25 ns (faster) | 33 ns | 25 ns (faster) | 45 ns (slower) | 25 ns (faster) | 25 ns |
| User I/O Lines | 64 | 64 | 64 | 64 | 64 | 64 | 64 (max 80) |
| Dedicated Inputs | 7 | 7 | 7 | 7 | 7 | 7 | 4 |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Temperature Grade | Commercial | Commercial | Military | Military | Commercial | Commercial | Industrial |
| Programming Tech | UV-erasable EEPROM | UV-erasable EEPROM | UV-erasable EEPROM | UV-erasable EEPROM | UV-erasable EEPROM | UV-erasable EEPROM | Electrically erasable (EE) |
主な差別化要因
- Largest macrocell count in the MAX 5000 PLCC family （vs EPM5192AJC84-15)
- Commercial vs military temperature grade option （vs EPM5192AGC84-20)
- 192 macrocells vs 128 in the closest cross-brand alternative （vs ATF1508ASL-25JI84)
設計ノート
Estimated: at 66.7 MHz toggle rate on 64 outputs with 50 pF load, the EPM5192AJC84-20 draws roughly 300–450 mA from its 5 V rail. Place one 0.1 uF ceramic decoupling capacitor within 5 mm of every VCC pin (pins 42, 56) plus a single 10 uF tantalum bulk capacitor near the package. Power-rail inductance must be minimized because the 5 V CMOS UV-erasable process is sensitive to Vcc droop below 4.75 V during high-speed switching.
The 84-pin PLCC J-Lead accepts both through-hole socket (e.g. Mill-Max 84-pin PLCC socket) and reflow-soldered surface mounting. For high-vibration industrial/military boards, use a PLCC socket with retention clips or add epoxy staking at the four corners. Keep all signal traces shorter than 50 mm to stay below the 33 ns tpd budget at full 66.7 MHz fmax, and use a continuous ground plane on layer 2 to provide a low-impedance return path.
Do NOT use this CPLD as a drop-in for the EPM5192AJC-25 (slower) unless timing closure is verified - the -20 grade is faster than -25 and any re-spin must keep the timing margin conservative. Also avoid substituting the ATF1508ASL-25JI84 without re-validating, because the 128 macrocells (vs 192) and 4 dedicated inputs (vs 7) may not match the original design. The UV window must be covered with an opaque label once the design is finalized, otherwise ambient UV will erase the configuration over time.
The EPM5192AJC84-20 has 5 V CMOS outputs with a typical 24 mA drive strength; for signals longer than 25 mm on FR-4, add 22–33 ohm series damping resistors at the source to suppress ringing. Clock and OE signals should use the dedicated input pins (pin 22 for global clock) rather than I/O pins to minimize skew. Estimated: at full 64-output simultaneous switching, ground-bounce may reach 0.8 V - keep sensitive analog grounds separated by at least 5 mm from PLCC ground pins.
コンプライアンス情報
EPM5192AJC84-20 is a legacy Altera MAX 5000 PLD released before RoHS-REACH enforcement; compliance status not published. Use the EPM5192AGC84-20 military variant for defense programs that require full material disclosure. RoHS-compliant equivalent not available from Altera.
