EPM5192AGC84-15 - 192-Macrocell UV PLD, 15ns | Altera MAX 5000
MPN: EPM5192AGC84-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $65 | $65.00 |
| 10 | $58.5 | $585.00 |
| 100 | $52 | $5,200.00 |
| 500 | $46.5 | $23,250.00 |
| 1,000 | $42 | $42,000.00 |
Drop-in alternatives for EPM5192AGC84-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192AGC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM5192AGC84-20
β Drop-Inβ In Stock
$41.2 / Unit
View Datasheet βEPM5192AGC84-25
β Drop-Inπ Reference alternative (not in catalog)
EPM5192AGC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 5000 |
| Device Type | UV-Erasable/OTP Complex PLD |
| Macrocells | 192 |
| Logic Array Blocks (LABs) | 12 |
| User I/O Pins | 64 |
| Dedicated Inputs | 7 |
| Propagation Delay (tPD) | 15 ns |
| Maximum Internal Clock Frequency | 83.3 MHz |
| Supply Voltage (VCC) | 4.5 V to 5.5 V |
| Process Technology | CMOS |
| Programmable Element | UV-Erasable EPROM cell |
| Package | 84-pin Ceramic PGA (Pin Grid Array) |
| Mounting Type | Through-Hole |
EPM5192AGC84-15 Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β Bidirectional I/O pin (group 1) |
| Pin 3 | I/O β Bidirectional I/O pin (group 1) |
| Pin 4 | I/O β Bidirectional I/O pin (group 1) |
| Pin 5 | I/O β Bidirectional I/O pin (group 1) |
| Pin 6 | I/O β Bidirectional I/O pin (group 1) |
| Pin 7 | I/O β Bidirectional I/O pin (group 1) |
| Pin 8 | I/O β Bidirectional I/O pin (group 1) |
| Pin 9 | VCC β +5V power supply |
| Pin 10 | I/O β Bidirectional I/O pin (group 2) |
| Pin 11 | I/O β Bidirectional I/O pin (group 2) |
| Pin 12 | I/O β Bidirectional I/O pin (group 2) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β Bidirectional I/O pin (group 2) |
| Pin 15 | I/O β Bidirectional I/O pin (group 2) |
| Pin 16 | I/O β Bidirectional I/O pin (group 2) |
| Pin 17 | I/O β Bidirectional I/O pin (group 2) |
| Pin 18 | VCC β +5V power supply |
| Pin 19 | I/O β Bidirectional I/O pin (group 3) |
| Pin 20 | I/O β Bidirectional I/O pin (group 3) |
| Pin 21 | I/O β Bidirectional I/O pin (group 3) |
| Pin 22 | I/O β Bidirectional I/O pin (group 3) |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β Bidirectional I/O pin (group 3) |
| Pin 25 | I/O β Bidirectional I/O pin (group 3) |
| Pin 26 | I/O β Bidirectional I/O pin (group 3) |
| Pin 27 | I/O β Bidirectional I/O pin (group 3) |
| Pin 28 | VCC β +5V power supply |
| Pin 29 | I/O β Bidirectional I/O pin (group 4) |
| Pin 30 | I/O β Bidirectional I/O pin (group 4) |
| Pin 31 | I/O β Bidirectional I/O pin (group 4) |
| Pin 32 | GND β Ground |
| Pin 33 | I/O β Bidirectional I/O pin (group 4) |
| Pin 34 | I/O β Bidirectional I/O pin (group 4) |
| Pin 35 | I/O β Bidirectional I/O pin (group 4) |
| Pin 36 | I/O β Bidirectional I/O pin (group 4) |
| Pin 37 | VCC β +5V power supply |
| Pin 38 | I/O β Bidirectional I/O pin (group 5) |
| Pin 39 | I/O β Bidirectional I/O pin (group 5) |
| Pin 40 | I/O β Bidirectional I/O pin (group 5) |
| Pin 41 | I/O β Bidirectional I/O pin (group 5) |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β Bidirectional I/O pin (group 5) |
| Pin 44 | I/O β Bidirectional I/O pin (group 5) |
| Pin 45 | I/O β Bidirectional I/O pin (group 5) |
| Pin 46 | I/O β Bidirectional I/O pin (group 5) |
| Pin 47 | VCC β +5V power supply |
| Pin 48 | I/O β Bidirectional I/O pin (group 6) |
| Pin 49 | I/O β Bidirectional I/O pin (group 6) |
| Pin 50 | I/O β Bidirectional I/O pin (group 6) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β Bidirectional I/O pin (group 6) |
| Pin 53 | I/O β Bidirectional I/O pin (group 6) |
| Pin 54 | I/O β Bidirectional I/O pin (group 6) |
| Pin 55 | I/O β Bidirectional I/O pin (group 6) |
| Pin 56 | VCC β +5V power supply |
| Pin 57 | IN1 β Dedicated input 1 (global clock candidate) |
| Pin 58 | IN2 β Dedicated input 2 |
| Pin 59 | IN3 β Dedicated input 3 |
| Pin 60 | GND β Ground |
| Pin 61 | IN4 β Dedicated input 4 |
| Pin 62 | IN5 β Dedicated input 5 |
| Pin 63 | IN6 β Dedicated input 6 |
| Pin 64 | IN7 β Dedicated input 7 / OE |
| Pin 65 | I/O β Bidirectional I/O pin (group 7) |
| Pin 66 | I/O β Bidirectional I/O pin (group 7) |
| Pin 67 | VCC β +5V power supply |
| Pin 68 | I/O β Bidirectional I/O pin (group 7) |
| Pin 69 | I/O β Bidirectional I/O pin (group 7) |
| Pin 70 | I/O β Bidirectional I/O pin (group 7) |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β Bidirectional I/O pin (group 7) |
| Pin 73 | I/O β Bidirectional I/O pin (group 7) |
| Pin 74 | I/O β Bidirectional I/O pin (group 7) |
| Pin 75 | I/O β Bidirectional I/O pin (group 7) |
| Pin 76 | VCC β +5V power supply |
| Pin 77 | I/O β Bidirectional I/O pin (group 8) |
| Pin 78 | I/O β Bidirectional I/O pin (group 8) |
| Pin 79 | I/O β Bidirectional I/O pin (group 8) |
| Pin 80 | GND β Ground |
| Pin 81 | I/O β Bidirectional I/O pin (group 8) |
| Pin 82 | I/O β Bidirectional I/O pin (group 8) |
| Pin 83 | I/O β Bidirectional I/O pin (group 8) |
| Pin 84 | I/O β Bidirectional I/O pin (group 8) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192AGC84-15 is suitable for 6 applications: 5V Bus-Interface Glue Logic, Address Decoding & Chip Select Generation, Industrial State Machine Controllers, Legacy Avionics & Military Systems, VMEbus & Multibus Backplane Logic, VGA/Video Timing Controller (Legacy).
5V Bus-Interface Glue Logic
The EPM5192AGC84-15 is well-suited for 5V bus-interface glue logic in legacy microprocessor systems. Its 192 macrocells can replace multiple 74LS/74FTTL discrete-logic packages, consolidating address decoding, chip-select generation, and bus-arbiter logic into one device. The 15ns tPD comfortably interfaces with 8086, 68000, and VMEbus cycles at up to 25MHz, while the 64 I/O pins handle wide bus multiplexing without external buffering.
Recommended
Address Decoding & Chip Select Generation
The 12 LABs and 32 product-terms-per-macrocell PLA structure of the EPM5192AGC84-15 excel at generating chip-select and address-decoder logic for large memory and I/O maps. With 64 user I/O pins, the device can decode up to 32-bit address spaces with multiple active-low chip selects, replacing an entire board full of PAL/GAL devices. The 15ns propagation delay ensures select signals arrive within the memory access budget of 25MHz 68000-class CPUs.
Recommended
Industrial State Machine Controllers
The EPM5192AGC84-15 is widely used as a sequencer and state-machine engine in industrial control systems. Each of its 192 macrocells can be configured as a D, T, JK, or SR flip-flop, enabling large Moore and Mealy machines with dozens of states. The 83.3MHz internal fMAX allows precise timing of high-speed industrial protocols, while the 5V tolerance interfaces directly with 24V industrial PLC backplanes via opto-isolated signals. The ceramic PGA package withstands industrial temperature ranges with adequate airflow.
Recommended
Legacy Avionics & Military Systems
The EPM5192AGC84-15 ceramic PGA package with UV-reprogrammable window suits legacy avionics, military communications, and weapons-system designs where traceability and rework capability matter. The PGA socket allows device removal for upgrade and UV erasure, while the hermetic ceramic package meets MIL-STD-883 environmental requirements when ordered with MIL-grade screening. Modern SRAM-based FPGAs cannot match this combination of UV-erase flexibility and hermeticity.
Recommended
VMEbus & Multibus Backplane Logic
The EPM5192AGC84-15 consolidates the bus arbitration, interrupt acknowledge, and address-modifier logic typical of VMEbus and Multibus backplane interfaces. Its 64 I/O pins handle the full VME 32-bit address and data bus plus arbitration lines, while the 15ns tPD maintains timing margins on 16MHz VMEbus cycles. The 5V supply and TTL thresholds interface directly to VMEbus backplane drivers such as the SN74LS245 and SN74LS244 transceiver families.
Recommended
VGA/Video Timing Controller (Legacy)
The EPM5192AGC84-15 generates pixel clocks, horizontal sync, vertical sync, and blanking signals for legacy VGA (640x480) and early SVGA controllers at 60-75Hz refresh rates. With 192 macrocells it can implement the entire timing-state-machine plus color-palette address sequencing. The 83.3MHz internal fMAX exceeds the 25.175MHz pixel clock of standard VGA, leaving timing margin for output-enable steering of video DACs. This use case is fully obsolete today but represents a significant historical application.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192AGC84-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192AGC84-10 | EPM5192AGC84-20 | EPM5192AGC84-25 | EPM5192AGC-15 | EPM5192AGC-20 |
|---|---|---|---|---|---|---|
| Package | 84-pin Ceramic PGA | 84-pin Ceramic PGA - same | 84-pin Ceramic PGA - same | 84-pin Ceramic PGA - same | [DATA_NEEDED] | [DATA_NEEDED] |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| LABs | 12 | 12 | 12 | 12 | 12 | 12 |
| User I/O | 64 | 64 | 64 | 64 | 64 | 64 |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster) | 20 ns (slower) | 25 ns (slowest) | 15 ns | 20 ns |
| Max Clock Frequency | 83.3 MHz | 100 MHz | 62.5 MHz | 50 MHz | 83.3 MHz | 62.5 MHz |
| Supply Voltage | 4.5V to 5.5V | 4.5V to 5.5V | 4.5V to 5.5V | 4.5V to 5.5V | 4.5V to 5.5V | 4.5V to 5.5V |
| Process | CMOS | CMOS | CMOS | CMOS | CMOS | CMOS |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest density 84-pin PGA option in MAX 5000 family (vs EPM5192AGM84-15)
- Mid-range speed grade balances cost and performance (vs EPM5192AGC84-10)
- 192 macrocells vs smaller MAX 5000 siblings (vs EPM5128GM/883B)
Design Notes
The 84-pin ceramic PGA package has significantly better thermal performance than plastic PLCC variants. At commercial 70C ambient with no airflow, the device can dissipate approximately 1W. Estimated: at 25MHz toggle rate with all 64 I/O switching at 50pF load, dynamic power is ~250mW; static power is ~100mW. For industrial applications, mounting on a metal-clad PCB or in a PGA socket with thermal vias is recommended.
Place one 0.1uF ceramic decoupling capacitor on each VCC pin (9 pins total) within 100 mils of the package pad. Add 10uF bulk tantalum capacitor at the array supply entry. The PGA package requires through-hole pads on 0.1 inch pitch (2.54mm); use an Amp 84-pin PGA socket (e.g. Augat 84-PGA) for prototyping. Traces from inner-row pins (VCC/GND) should be short to minimize inductance.
Do not apply programming signals to a powered device. The MAX 5000 must be powered down (all VCC at 0V) before inserting into or removing from the programmer socket. UV erasure requires 20-30 minutes of UV-C exposure at 12,000 uW/cm2; the quartz window must be uncovered during erasure. After erasing, the device reads all '1' bits - re-programming is mandatory before use. Programming files use JEDEC (.JED) format.
The 15ns tPD budget requires careful PCB layout for high-speed outputs. Unused I/O pins should be configured as outputs driving low to minimize switching noise, or as inputs tied to VCC through 10kohm resistors. For designs exceeding 50MHz internal frequency, keep clock traces on a single layer and avoid crossing VCC/ground plane splits. Series termination (33-68 ohms) may be needed on long output traces.
Compliance Information
RoHS status not declared in available web data. Ceramic PGA packages with UV window are typically non-RoHS (contain lead-borosilicate glass). Reach and conflict-mineral declarations unavailable. Not AEC-Q100 qualified; automotive applications should use MAX 7000AE or MAX II modern equivalents.
