EPM5192ALC84-20 - Altera 192-Macrocell MAX 5000 EPLD | PLCC-84
部品番号: EPM5192ALC84-20 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $45 | $45.00 |
| 10 | $38.5 | $385.00 |
| 100 | $31.2 | $3,120.00 |
| 500 | $24.75 | $12,375.00 |
| 1,000 | $19.4 | $19,400.00 |
EPM5192ALC84-20 概要
A Complex PLD (CPLD) is a non-volatile, electrically programmable logic device that contains an array of AND/OR macrocell logic blocks interconnected by a global programmable interconnect matrix. In the system hierarchy, the CPLD sits between discrete SSI/MSI logic (gates, flip-flops) and the more recent SRAM-based FPGA; the EPM5192 specifically belongs to the EPLD subcategory (Erasable Programmable Logic Device), where configuration is stored in EPROM cells that can be erased only by UV exposure through a quartz window - a hallmark of the MAX 5000 era. This makes the part well-suited to production volumes where bitstream security and one-time-programmability are valued over in-field re-programmability.
Key features include 192 macrocells of user logic, the 20 ns pin-to-pin combinatorial delay (-20 speed grade), a CMOS process with TTL-compatible I/O, and the plastic J-lead PLCC-84 footprint that allows low-cost socket programming and field replacement. The MAX 5000 architecture integrates multiple Logic Array Blocks (LABs) with a centralized interconnect, providing deterministic timing that CPLDs are valued for - in contrast to the statistical routing delays of SRAM FPGAs, every EPM5192 signal path has a guaranteed worst-case delay.
Typical applications include legacy industrial control logic, glue logic replacement for vintage PC/AT motherboards and embedded controller boards, address decoding and bus interface logic, motor and stepper driver sequencing, and any design that was originally specified around a MAX 5000 series EPLD in the 1990s. Engineers maintaining long-life industrial and military platforms still depend on this part because the original design documentation, board layout, and timing closure were all done against the EPM5192 - substituting an unrelated CPLD family would require re-validating timing across every signal path.
When designing with this device, designers should note that the device is non-volatile only after EPROM programming, so any change requires UV erasure and reprogramming; modern JTAG-based ISP is not available on MAX 5000. For new designs, designers should evaluate whether a current-generation MAX II or MAX V CPLD (in a different package and pinout) offers better migration economics rather than specifying this mature legacy part.
This page synthesizes distributor pricing, a parametric comparison against pin-compatible MAX 5000 variants, and practical design notes not found in the manufacturer datasheet - information engineered to help buyers and legacy-system maintainers source and qualify the EPM5192ALC84-20 with confidence.
ドロップイン代替品: EPM5192ALC84-20 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM5192ALC84-20 （同一形状・フットプリント） — 相違点: Process Technology, Device Type, Package, Mounting Type, Propagation Delay (tPD).
クイック比較ツール — 並列比較する代替部品を選択:
EPM5192ALC84-15
✅ ドロップイン✓ 在庫あり
$13.2 / 個
データシートを見る →EPM5192AJC84-20
✅ ドロップイン✓ 在庫あり
$19.2 / 個
データシートを見る →EPM5192AJC84-15
✅ ドロップイン✓ 在庫あり
$18.95 / 個
データシートを見る →EPM5192AJI84-20
✅ ドロップイン✓ 在庫あり
$10.95 / 個
データシートを見る →EPM5128AGC84-20
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM5192ALC84-20 最大定格＆電気的特性
| Device Type | UV-Erasable/OTP Complex PLD (EPLD) |
| Series | Altera MAX 5000 |
| Macrocells | 192 |
| Process Technology | CMOS |
| Speed Grade | -20 (20 ns pin-to-pin delay) |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Terminal Pitch | 1.270 mm |
| Terminal Form | J-bend |
| Package Code | QCCJ (PLCC-84) |
| Package Shape | Square |
| Temperature Grade | Commercial |
| Programming Method | UV-erase + EPROM (One-Time-Programmable option) |
| Logic Family | MAX 5000 EPLD |
| I/O Compatibility | TTL-compatible |
| 実装タイプ | Surface Mount (PLCC socket-compatible) |
| Configuration Memory | EPROM (UV-erasable) |
EPM5192ALC84-20 ピン構成
| ピン 1 | I/O — User I/O pin |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | GND — Ground |
| ピン 14 | I/O — User I/O pin |
| ピン 15 | I/O — User I/O pin |
| ピン 16 | I/O — User I/O pin |
| ピン 17 | I/O — User I/O pin |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | I/O — User I/O pin |
| ピン 22 | I/O — User I/O pin |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | GND — Ground |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | GND — Ground |
| ピン 56 | I/O — User I/O pin |
| ピン 57 | I/O — User I/O pin |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | GND — Ground |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | GND — Ground |
| ピン 84 | VCC — Supply voltage (+5 V) |
主な用途
EPM5192ALC84-20 の用途: 6 件s: Legacy Industrial Control Logic, Vintage PC/AT Motherboard Glue Logic, Motor Driver Sequencing and Control, Embedded Controller Board Glue Logic, Address Decoding and Bus Interface Logic, Legacy Avionics and Military Logic Replacement.
Legacy Industrial Control Logic
The EPM5192ALC84-20's 192 macrocells and 20 ns deterministic timing make it ideal for legacy industrial control boards originally designed around the MAX 5000 family in the early 1990s. The 192-macrocell capacity accommodates substantial glue logic - address decoding for ISA/PCI bus peripherals, motor-driver sequencing, and PLC-style state machines - in a single device, replacing 8-15 discrete SSI/MSI packages. Deterministic pin-to-pin delay ensures timing closure holds across the commercial 0C-70C range without re-qualification, which is critical for industrial customers running long-life platforms (15-25 years). The PLCC-84 socket allows field replacement and reprogramming via UV erase in a windowed variant, supporting maintenance cycles on deployed equipment.
おすすめ
Vintage PC/AT Motherboard Glue Logic
The EPM5192ALC84-20 was widely specified on vintage PC/AT, VLB, and early PCI motherboards for address decoding, bus arbitration, and DRAM control logic. The 192 macrocells easily absorb the address decoding for an entire bank of ISA peripherals plus BIOS shadow mapping, while the 20 ns pin-to-pin delay comfortably meets the ISA bus 8 MHz timing budget with margin. The PLCC-84 package allowed socket-based assembly during motherboard production, supporting field serviceability when a logic revision was needed. Modern retro-computing enthusiasts and industrial PC manufacturers maintaining legacy x86 platforms depend on this part to keep service contracts alive on equipment that cannot be redesigned without disrupting customer operations.
おすすめ
Motor Driver Sequencing and Control
The EPM5192ALC84-20 serves as the central state machine for stepper and brushless DC motor driver boards, where its 192 macrocells can encode multi-phase commutation tables, PWM generation logic, and fault-handling state machines in a single chip. The deterministic 20 ns delay supports high-RPM commutation timing without jitter, while the TTL-compatible I/O interfaces directly to optocouplers and gate drivers without level shifters. Industrial motor control applications also benefit from the part's commercial temperature rating and proven long-term availability in the surplus/broker market. Engineers maintaining CNC retrofit kits and industrial automation equipment value the EPM5192 for its ability to replace multiple 74LS-series logic chips with one programmable device on the same PCB footprint.
おすすめ
Embedded Controller Board Glue Logic
Embedded single-board computers (SBCs) and microcontroller add-in boards from the 1990s and early 2000s frequently use the EPM5192ALC84-20 as the central glue-logic device for chip-select generation, interrupt routing, and bus-width conversion. The 192-macrocell capacity absorbs the entire peripheral decoding tree plus custom I/O expansion logic, while the 84-pin PLCC package provides enough I/O for typical 8-16 chip-select designs. The non-volatile EPROM configuration means the board boots to a known-good state even after years of storage, a major advantage over SRAM-based FPGAs that lose configuration on power-down. Embedded systems manufacturers with long-term supply contracts still specify this part for after-sales replacement stock.
おすすめ
Address Decoding and Bus Interface Logic
The EPM5192ALC84-20 is a classic choice for address decoding and bus interface logic in multi-master systems, where 192 macrocells can decode the full 24-bit address space of an 80286/80386 system plus generate wait-state timing and bus arbitration signals. The 20 ns pin-to-pin delay meets ISA and VLB bus timing requirements with comfortable margin, and the deterministic routing of the MAX 5000 architecture eliminates the timing uncertainty that plagues SRAM-FPGA implementations. Telecom and industrial-control boards with proprietary backplane buses often specify this part for its proven timing closure, and the PLCC-84 package supports socketed assembly for prototype iteration. Modern retro-computing and industrial-control customers continue sourcing this part for legacy system maintenance.
おすすめ
Legacy Avionics and Military Logic Replacement
The EPM5192ALC84-20 is occasionally specified in legacy avionics, military, and aerospace platforms that were qualified against the MAX 5000 family in the 1990s and where re-design certification cost exceeds part cost. The 192-macrocell capacity and 20 ns timing support mission-critical logic functions in flight control, navigation, and communications subsystems on platforms with 20-30 year service lives. While the commercial-grade EPM5192ALC84-20 is the most common variant, military-temperature (M-grade) screened versions of the same die are available on the broker market for high-reliability applications. Long-life aerospace programs rely on this part for after-market support and re-spares, since the alternative is full board re-design and re-certification - a multi-million-dollar proposition.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM5192ALC84-20 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM5192ALC84-15 | EPM5192AJC84-20 | EPM5192AJC84-15 | EPM5192AJI84-20 | EPM5128AGC84-20 |
|---|---|---|---|---|---|---|
| Package | PLCC-84 | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same | PLCC-84 - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 128 (-33%) |
| Speed Grade | -20 (20 ns) | -15 (15 ns, -25%) | -20 (20 ns) | -15 (15 ns) | -20 (20 ns) | -20 (20 ns) |
| Temperature Grade | Commercial | Commercial | Commercial | Commercial | Industrial | Commercial |
| Configuration Memory | EPROM (UV-erasable) | EPROM (UV-erasable) | EPROM (UV-erasable) | EPROM (UV-erasable) | EPROM (UV-erasable) | EPROM (UV-erasable) |
| Series | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Terminal Pitch | 1.270 mm | 1.270 mm | 1.270 mm | 1.270 mm | 1.270 mm | 1.270 mm |
主な差別化要因
- Higher macrocell count than MAX 5000 mid-range variants （vs EPM5128AGC84-20)
- Industrial temperature variant available on same pinout （vs EPM5192AJI84-20)
- Faster speed grade available on same pinout （vs EPM5192ALC84-15)
設計ノート
The plastic PLCC-84 package (L-suffix) of the EPM5192ALC84-20 has no UV erase window, making it strictly One-Time-Programmable (OTP). Any design error in the JEDEC fuse map requires physically replacing the chip - unlike modern EEPROM- or flash-based CPLDs that support in-system reprogramming. Engineers prototyping with this part should order a windowed ceramic variant (if available on the broker market) for development, then move to the plastic OTP version for production to control cost. Programming must be done via an Altera-compatible programming unit (e.g., Altera Logic Programmer) supporting the MAX 5000 JEDEC format - third-party universal programmers may require device-specific adapters.
Use a low-profile PLCC-84 through-hole socket (e.g., 3M Textool or similar) rather than soldering the EPM5192ALC84-20 directly to the PCB. This allows field replacement when the OTP device needs to be swapped, supports engineering rework during prototype bring-up, and accommodates programming-iteration cycles on production boards. Verify the socket's J-bend terminal geometry matches the 1.270 mm pitch and the plastic carrier's lead thickness; sockets rated for industrial temperature (-40C to +85C) are recommended for harsh-environment deployments. Maintain 0.1uF decoupling capacitors on every VCC pin pair (the EPM5192 has multiple VCC/GND pins distributed around the package) placed within 5 mm of the package body.
The EPM5192ALC84-20 is a 5V TTL-compatible CMOS part designed for the pre-3.3V era, with output edges that exhibit significant ringing when driving long PCB traces. For bus-interface designs, series-terminate each output with 33-ohm resistors to dampen reflections on traces longer than 50 mm, and avoid using the same I/O bank for high-speed and slow signals to prevent cross-talk. The 20 ns pin-to-pin delay means the part cannot reliably toggle faster than ~25 MHz on combinatorial paths; flip-flop-based registered designs can reach higher toggle rates, but verify against the MAX 5000 datasheet timing chapter for the specific register-to-PAD path. For legacy designs migrating from earlier 74F/74AS TTL logic, replace the discrete gates one-for-one and verify the fanout budget per I/O bank.
コンプライアンス情報
Compliance data not present in verified web data - the original Altera MAX 5000 datasheet predates RoHS documentation. As a plastic PLCC part manufactured in the 1990s, the original EPM5192ALC84-20 was likely lead-bearing and not RoHS-compliant; lead-free RoHS-compliant versions may be available from brokers as factory-direct or refurbished stock but cannot be confirmed from the provided data.