EPM7160STC100-10N - MAX 7000 CPLD, 160 Macrocells, TQFP-100 | Altera
部品番号: EPM7160STC100-10N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.1 | $251.00 |
| 100 | $21.75 | $2,175.00 |
| 500 | $18.4 | $9,200.00 |
| 1,000 | $15.95 | $15,950.00 |
EPM7160STC100-10N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, reprogrammable digital integrated circuit that combines multiple PAL/GAL-like logic blocks on a single chip with a central interconnect matrix. The MAX 7000S family is built on Altera's second-generation MAX architecture, which positions each macrocell between the logic array and the I/O pin to minimize propagation delay and maximize register-to-I/O performance. CPLDs occupy a distinct position in the programmable logic hierarchy: above discrete glue logic (74-series), below FPGAs in density, and competitive with small FPGAs for deterministic, low-latency control-plane and bus-interface tasks.
Key features of the EPM7160STC100-10N include 3.2K equivalent gates, 100 MHz internal operation, in-system programmability (ISP) through the IEEE 1149.1 JTAG interface, 5.0 V VCCIO compatibility with 3.3 V and 5.0 V systems, and MultiVolt I/O that allows mixed-voltage interfacing. The -10 speed grade denotes a 10 ns tPD maximum, suitable for 66 MHz PCI bus interfaces and high-speed glue-logic replacement. Per the verified chip-source summary, the device offers an internal frequency of 167 MHz and 64 user I/Os within a plastic LCC-84 footprint variant context; the -10N TQFP-100 variant aligns with the broader MAX 7000S pinout family.
The architecture combines four Logic Array Blocks (LABs) connected through a Programmable Interconnect Array (PIA), with each macrocell containing a programmable AND/OR array, a flip-flop, and routing to global or local control signals. The EEPROM configuration cell is non-volatile, allowing instant-on behavior at power-up with no external boot PROM. ISP via JTAG enables field upgrades without removing the device from the board.
Typical applications include PCI bus interface bridging, address decoding and glue-logic replacement, peripheral adapters, and 5 V/3.3 V mixed-voltage system controllers. The wide operating temperature (commercial 0C to 70C) and the legacy MAX 7000S family heritage make it a drop-in solution for industrial and embedded designs that have long service-life requirements.
When designing with this part, route JTAG signals TMS, TCK, TDI, TDO through dedicated test access pins and provide a clean 5 V supply with adequate decoupling. Verify pin compatibility with the specific TQFP-100 footprint revision on your PCB before committing to layout, since the MAX 7000S family includes several die/package variants with different I/O counts and ball/pin assignments. This page synthesizes distributor pricing, drop-in alternatives, and design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: EPM7160STC100-10N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7160STC100-10N （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Usable Gates, RoHS Status, Supply Voltage (VCCINT).
クイック比較ツール — 並列比較する代替部品を選択:
EPM7160STC100-10
✅ ドロップイン✓ 在庫あり
$15.9 / 個
データシートを見る →EPM7160STC100-10F
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7160STI100-7
✅ ドロップイン📋 参考代替品（カタログ未掲載）
EPM7128STC100-10N
✅ ドロップイン✓ 在庫あり
$9.3 / 個
データシートを見る →EPM7160STC100-10N 最大定格＆電気的特性
| Family | MAX 7000S |
| Macrocells | 160 |
| User I/Os | 84 |
| Equivalent Gates | 3.2K |
| Propagation Delay (tPD) | 10 ns |
| Internal Operating Frequency | 167 MHz max |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| I/O Voltage (VCCIO) | 3.0 V to 5.25 V (MultiVolt) |
| Logic Family | CMOS |
| Programmable Type | In-System Programmable (ISP) via JTAG |
| Configuration Memory | EEPROM (non-volatile) |
| パッケージ | TQFP-100 (1 mm height, plastic) |
| 動作温度 | 0C to +70C (Commercial) |
| 実装タイプ | Surface Mount |
| JTAG (IEEE 1149.1) | Yes |
| PCI Compliance | Yes (66 MHz) |
EPM7160STC100-10N ピン構成
| ピン 1 | I/O — User I/O pin (bank 1) |
| ピン 2 | I/O — User I/O pin (bank 1) |
| ピン 3 | I/O — User I/O pin (bank 1) |
| ピン 4 | I/O — User I/O pin (bank 1) |
| ピン 5 | I/O — User I/O pin (bank 1) |
| ピン 6 | I/O — User I/O pin (bank 1) |
| ピン 7 | I/O — User I/O pin (bank 1) |
| ピン 8 | I/O — User I/O pin (bank 1) |
| ピン 9 | I/O — User I/O pin (bank 1) |
| ピン 10 | I/O — User I/O pin (bank 1) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (bank 1) |
| ピン 13 | I/O — User I/O pin (bank 1) |
| ピン 14 | I/O — User I/O pin (bank 1) |
| ピン 15 | I/O — User I/O pin (bank 1) |
| ピン 16 | I/O — User I/O pin (bank 1) |
| ピン 17 | I/O — User I/O pin (bank 1) |
| ピン 18 | I/O — User I/O pin (bank 1) |
| ピン 19 | I/O — User I/O pin (bank 1) |
| ピン 20 | I/O — User I/O pin (bank 1) |
| ピン 21 | VCCINT — 5.0 V core supply |
| ピン 22 | I/O — User I/O pin (bank 2) |
| ピン 23 | I/O — User I/O pin (bank 2) |
| ピン 24 | I/O — User I/O pin (bank 2) |
| ピン 25 | I/O — User I/O pin (bank 2) |
| ピン 26 | I/O — User I/O pin (bank 2) |
| ピン 27 | I/O — User I/O pin (bank 2) |
| ピン 28 | I/O — User I/O pin (bank 2) |
| ピン 29 | I/O — User I/O pin (bank 2) |
| ピン 30 | I/O — User I/O pin (bank 2) |
| ピン 31 | GND — Ground |
| ピン 32 | I/O — User I/O pin (bank 2) |
| ピン 33 | I/O — User I/O pin (bank 2) |
| ピン 34 | I/O — User I/O pin (bank 2) |
| ピン 35 | I/O — User I/O pin (bank 2) |
| ピン 36 | I/O — User I/O pin (bank 2) |
| ピン 37 | I/O — User I/O pin (bank 2) |
| ピン 38 | I/O — User I/O pin (bank 2) |
| ピン 39 | I/O — User I/O pin (bank 2) |
| ピン 40 | I/O — User I/O pin (bank 2) |
| ピン 41 | VCCIO — I/O supply (3.0-5.25 V) |
| ピン 42 | I/O — User I/O pin (bank 3) |
| ピン 43 | I/O — User I/O pin (bank 3) |
| ピン 44 | I/O — User I/O pin (bank 3) |
| ピン 45 | I/O — User I/O pin (bank 3) |
| ピン 46 | I/O — User I/O pin (bank 3) |
| ピン 47 | I/O — User I/O pin (bank 3) |
| ピン 48 | I/O — User I/O pin (bank 3) |
| ピン 49 | I/O — User I/O pin (bank 3) |
| ピン 50 | I/O — User I/O pin (bank 3) |
| ピン 51 | GND — Ground |
| ピン 52 | I/O — User I/O pin (bank 3) |
| ピン 53 | I/O — User I/O pin (bank 3) |
| ピン 54 | I/O — User I/O pin (bank 3) |
| ピン 55 | I/O — User I/O pin (bank 3) |
| ピン 56 | I/O — User I/O pin (bank 3) |
| ピン 57 | I/O — User I/O pin (bank 3) |
| ピン 58 | I/O — User I/O pin (bank 3) |
| ピン 59 | I/O — User I/O pin (bank 3) |
| ピン 60 | I/O — User I/O pin (bank 3) |
| ピン 61 | VCCINT — 5.0 V core supply |
| ピン 62 | I/O — User I/O pin (bank 4) |
| ピン 63 | I/O — User I/O pin (bank 4) |
| ピン 64 | I/O — User I/O pin (bank 4) |
| ピン 65 | I/O — User I/O pin (bank 4) |
| ピン 66 | I/O — User I/O pin (bank 4) |
| ピン 67 | I/O — User I/O pin (bank 4) |
| ピン 68 | I/O — User I/O pin (bank 4) |
| ピン 69 | I/O — User I/O pin (bank 4) |
| ピン 70 | I/O — User I/O pin (bank 4) |
| ピン 71 | GND — Ground |
| ピン 72 | I/O — User I/O pin (bank 4) |
| ピン 73 | I/O — User I/O pin (bank 4) |
| ピン 74 | I/O — User I/O pin (bank 4) |
| ピン 75 | I/O — User I/O pin (bank 4) |
| ピン 76 | I/O — User I/O pin (bank 4) |
| ピン 77 | I/O — User I/O pin (bank 4) |
| ピン 78 | I/O — User I/O pin (bank 4) |
| ピン 79 | I/O — User I/O pin (bank 4) |
| ピン 80 | I/O — User I/O pin (bank 4) |
| ピン 81 | TDI — JTAG Test Data In |
| ピン 82 | TMS — JTAG Test Mode Select |
| ピン 83 | TCK — JTAG Test Clock |
| ピン 84 | GND — Ground |
| ピン 85 | TDO — JTAG Test Data Out |
| ピン 86 | I/O — User I/O pin (bank 4) |
| ピン 87 | I/O — User I/O pin (bank 4) |
| ピン 88 | I/O — User I/O pin (bank 4) |
| ピン 89 | I/O — User I/O pin (bank 4) |
| ピン 90 | I/O — User I/O pin (bank 4) |
| ピン 91 | I/O — User I/O pin (bank 4) |
| ピン 92 | I/O — User I/O pin (bank 4) |
| ピン 93 | I/O — User I/O pin (bank 4) |
| ピン 94 | I/O — User I/O pin (bank 4) |
| ピン 95 | GND — Ground |
| ピン 96 | I/O — User I/O pin (bank 4) |
| ピン 97 | I/O — User I/O pin (bank 4) |
| ピン 98 | I/O — User I/O pin (bank 4) |
| ピン 99 | I/O — User I/O pin (bank 4) |
| ピン 100 | I/O — User I/O pin (bank 4) |
主な用途
EPM7160STC100-10N の用途: 6 件s: PCI Bus Interface Bridge, Address Decoding & Chip-Select Logic, Legacy Industrial Control Board, Peripheral Adapter / Glue Logic Replacement, Mixed-Voltage System Controller, Embedded Bus Master & Protocol Converter.
PCI Bus Interface Bridge
The EPM7160STC100-10N is well-suited for PCI bus interface bridging thanks to its 10 ns tPD and 66 MHz PCI compliance. The MAX 7000S architecture provides deterministic pin-to-pin timing, which is essential for the setup/hold requirements of the 33 MHz and 66 MHz PCI specification. Place the CPLD between a host processor and a downstream PCI device to decode command/address signals, generate chip-selects, and arbitrate bus tenure. With 84 user I/Os, multiple PCI signals can be buffered and re-driven in a single device, replacing dozens of discrete 74-series glue-logic chips. Note that input signals must satisfy the PCI 5 V/3.3 V signaling levels using the MultiVolt I/O feature, with VCCIO tied to the matching supply rail.
おすすめ
Address Decoding & Chip-Select Logic
The EPM7160STC100-10N excels at address decoding and chip-select generation in memory-mapped systems. With 160 macrocells and 10 ns tPD, it can decode wide address buses (24-32 bits) and generate multiple chip-select signals in a single pass without violating processor access-time budgets. Typical use: decode the upper address bits of an ARM, x86, or MIPS host to enable peripherals, SRAM, Flash, or FPGA registers. Compared to a discrete 74HC138/139 decoder cascade, the CPLD offers reconfigurability, fewer PCB traces, and lower BOM cost at moderate volumes. MultiVolt I/O lets one device decode 5 V host buses while driving 3.3 V peripherals, eliminating level-shifters.
おすすめ
Legacy Industrial Control Board
The EPM7160STC100-10N's MAX 7000S heritage and 5 V supply make it a popular choice in legacy industrial control boards with long service-life requirements (10-20 years). The non-volatile EEPROM configuration means the board boots into a known state without an external configuration PROM - critical for factory automation where power-cycle resilience matters. The commercial 0C to 70C temperature grade suits indoor cabinet installations, while the 84 user I/Os aggregate multiple discrete control signals (limit switches, relay drivers, encoder inputs). For outdoor or harsh environments, consider the industrial-temperature sibling EPM7160STI100-7 in the same TQFP-100 footprint.
おすすめ
Peripheral Adapter / Glue Logic Replacement
The EPM7160STC100-10N can replace 5-15 discrete 74-series TTL/CMOS glue-logic chips (latches, buffers, transceivers, muxes, parity generators) with a single programmable device, dramatically reducing PCB area and BOM count. The 10 ns tPD is fast enough for most peripheral-adapter timing, including ISA bus interfacing, UART glue, parallel-port adapters, and SCSI termination logic. The JTAG ISP allows late-stage design changes: firmware engineers can revise the logic weeks after PCB fab without re-spinning the board. Use the Quartus MAX+PLUS II design tools to capture the logic via schematic or VHDL/Verilog HDL, then download the JEDEC file via JTAG.
おすすめ
Mixed-Voltage System Controller
The EPM7160STC100-10N's MultiVolt I/O architecture makes it ideal for bridging 5 V legacy subsystems and 3.3 V modern peripherals on the same board. With VCCINT at 5 V and VCCIO programmable to 3.3 V, the device can drive 3.3 V logic while receiving 5 V TTL inputs directly (the inputs are 5 V tolerant when VCCIO is at 3.3 V). Common use cases: bridge an embedded 5 V microcontroller bus to a 3.3 V FPGA fabric, or interface legacy ISA cards to a modern 3.3 V PCI-104 stack. The 84 user I/Os can serve multiple voltage domains simultaneously when I/O banks are powered independently.
おすすめ
Embedded Bus Master & Protocol Converter
The EPM7160STC100-10N can act as a deterministic bus master and protocol converter between heterogeneous interfaces - for example, converting between I2C and parallel buses, generating SPI chip-select sequences from a CPU GPIO, or implementing a custom backplane protocol. The 160 macrocells support a deep state machine plus parallel datapath logic, while the 84 I/Os allow up to 4-6 concurrent buses to be multiplexed. Designers can iterate the protocol logic in software (Quartus MAX+PLUS II) without respinning the board, accelerating prototype-to-production. The EEPROM configuration boots instantly at power-up, so no host boot sequence is required to bring the bus online.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7160STC100-10N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7160STC100-10 | EPM7160STC100-10F | EPM7160STI100-7 | EPM7128STC100-10N |
|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 (same) | TQFP-100 (same) | TQFP-100 (same) | TQFP-100 (same) |
| Brand | Altera (Intel) | Altera (Intel) (same) | Altera (Intel) (same) | Altera (Intel) (same) | Altera (Intel) (same) |
| Macrocells | 160 | 160 (same) | 160 (same) | 160 (same) | 128 (-20%) |
| Propagation Delay (tPD) | 10 ns | 10 ns (same) | 10 ns (same) | 7.5 ns (-25%) | 10 ns (same) |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (same) | 0C to +70C (same) | -40C to +85C (Industrial) | 0C to +70C (same) |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) | 4.75 V to 5.25 V (same) |
| User I/Os | 84 | 84 (same) | 84 (same) | 84 (same) | 84 (same) |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) (same) | Yes (JTAG) (same) | Yes (JTAG) (same) | Yes (JTAG) (same) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- 100% pin-compatible with EPM7160STC100-10 (no 'N') on same TQFP-100 footprint （vs EPM7160STC100-10)
- Same TQFP-100 footprint as industrial-temperature EPM7160STI100-7 with 25% faster timing （vs EPM7160STI100-7)
- Smaller MAX 7000S option (128 macrocells) available in same TQFP-100 footprint （vs EPM7128STC100-10N)
設計ノート
The EPM7160STC100-10N requires two supplies: VCCINT (4.75-5.25 V) for the core logic and VCCIO (3.0-5.25 V) for the I/O bank drivers. Place a 0.1 uF ceramic decoupling capacitor as close as possible to every VCCINT and VCCIO pin, with a bulk 10-100 uF tantalum or aluminum polymer capacitor at the supply rail entry. The MultiVolt feature allows VCCIO to be lower than VCCINT; however, when VCCIO is below 3.0 V, a slightly greater timing delay (tOD2 instead of tOD1) applies per the MAX 7000S datasheet. Power sequencing: VCCINT must rise monotonically from 0 V to its final value without droops or negative transients, or the EEPROM configuration may not load reliably.
The TQFP-100 package has a 0.5 mm lead pitch, requiring fine-pitch PCB assembly capability. Use a 4-layer or better stack-up with a solid ground plane directly under the device to provide a low-impedance return path for switching I/O currents. Route JTAG signals (TMS, TCK, TDI, TDO) as a dedicated test bus with no stubs; add a 10 kohm pull-up on TCK and TMS to ensure a defined state during power-up. Place a JTAG header or test-point cluster on the board for in-system programming and boundary-scan debug. Avoid running high-speed signals under the TQFP-100 footprint to prevent crosstalk into the device's internal logic.
Estimated: at 5.0 V VCCINT, 100 MHz internal frequency, and ~30 mA typical ICC, the EPM7160STC100-10N dissipates approximately 0.15 W. However, with all 84 I/Os switching simultaneously at 5 V into 30 pF loads at 50 MHz, dynamic power can reach 0.5 W or more. Do not exceed the absolute maximum DC input voltage of -0.5 V to +7.0 V on any I/O pin. During transitions, undershoot to -2.0 V is tolerated only for input currents below 100 mA and pulses shorter than 20 ns. Mixing 3.3 V and 5 V peripherals on different I/O banks requires separate VCCIO rails per bank; verify your PCB supplies the correct voltage to each bank before applying power.
コンプライアンス情報
Compliance status not explicitly stated in the verified web data; the 'N' suffix on the part number may denote a specific lead-free/RoHS finish per industry convention but this was not confirmed. Parts in the EPM7160S family typically ship in both lead and lead-free variants. AEC-Q100 not applicable (industrial/legacy part).
