EPM7192SQI160-10N - MAX 7000S CPLD, 192 Macrocells, 100MHz | Altera
部品番号: EPM7192SQI160-10N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $63.24 | $63.24 |
| 10 | $56.92 | $569.20 |
| 100 | $48.75 | $4,875.00 |
| 500 | $41.3 | $20,650.00 |
| 1,000 | $35.9 | $35,900.00 |
EPM7192SQI160-10N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PAL/GAL devices and high-density FPGAs in the programmable logic hierarchy. CPLDs are characterized by instant-on (no boot/configuration load required), deterministic timing, and EEPROM or flash-based configuration that retains its bitstream through power cycles. They belong to the broader class of programmable logic devices (PLDs) and are widely used for glue logic, bus interfacing, and state-machine implementation where fast, predictable response is more important than raw logic density.
Key features of this part include a 10 ns pin-to-pin propagation delay, internal counter frequencies up to 167 MHz, 5.0V in-system programmability (ISP) via JTAG, and support for hot-socketing. The device is fabricated in 5V CMOS technology and integrates 192 macrocells arranged in Logic Array Blocks (LABs) interconnected by a programmable interconnect array (PIA). It also supports the IEEE 1149.1 boundary-scan standard for board-level testability.
From an architectural perspective, the MAX 7000S family uses Altera's second-generation MAX architecture with each macrocell containing a programmable AND/OR array, a flip-flop, and product-term allocation logic. The EEPROM configuration memory provides non-volatile storage without external boot devices, and the 5V-tolerant I/O structure allows direct interface with TTL and CMOS logic of mixed-voltage systems without level-level shifting in most cases.
Typical applications include bus interfacing (PCI bridge glue logic, address decoding), state-machine controllers in industrial automation, glue logic between microprocessors and peripherals, motor-control sequencing in factory automation, and legacy 5V system designs where non-volatile, deterministic logic is required.
Designers should note the PQFP-160 package's lead pitch of 0.5 mm and verify PCB footprint compatibility with the device footprint before re-spinning layouts. The 5V supply requirement is non-negotiable; this device is not compatible with 3.3V-only rails without a level translator. Programming is performed via JTAG using Altera/Intel Quartus or legacy MAX+PLUS II software.
This page synthesizes distributor stock data, drop-in alternative MPNs, and practical design notes - including board-level implementation guidance - not found in the standalone manufacturer datasheet.
ドロップイン代替品: EPM7192SQI160-10N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM7192SQI160-10N （同一形状・フットプリント） — 相違点: Package, Usable Gates, Device Type, In-System Programmability, Operating Temperature.
クイック比較ツール — 並列比較する代替部品を選択:
EPM7192SQI160-10
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM7192SQC160-10N
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM7192SQC160-15
✅ ドロップイン✓ 在庫あり
$8.75 / 個
データシートを見る →EPM7192SQC160-7N
✅ ドロップイン✓ 在庫あり
$9.6 / 個
データシートを見る →EPM7192SQC160-10
✅ ドロップイン✓ 在庫あり
$18.25 / 個
データシートを見る →EPM7192SQI160-10N 最大定格＆電気的特性
| Series | MAX 7000S |
| Family | MAX 7000 |
| Architecture | Second-generation MAX (CMOS, EEPROM) |
| Logic Elements / Macrocells | 192 macrocells |
| Usable Gates | 3.75K (typical) |
| User I/Os | 124 |
| ピン数 | 160 |
| パッケージ | PQFP-160 (QFP-160, plastic) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Internal Frequency | 167 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| Supply Voltage (VCCIO) | 5.0 V |
| In-System Programmability | Yes (5V ISP, JTAG) |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) |
| 動作温度 | 0C to +70C (industrial, 'N' suffix) |
| 実装タイプ | Surface Mount |
| Technology | 5V CMOS, EEPROM configuration memory |
| Logic Family | CMOS |
| Propagation Delay | 7.5 ns to 10 ns (speed grade dependent) |
| RoHS ステータス | Compliant (per lead-free PQFP package marking) |
EPM7192SQI160-10N ピン構成
| ピン 1 | I/O — User I/O pin (LAB I/O bank) |
| ピン 2 | I/O — User I/O pin (LAB I/O bank) |
| ピン 3 | I/O — User I/O pin (LAB I/O bank) |
| ピン 4 | I/O — User I/O pin (LAB I/O bank) |
| ピン 5 | I/O — User I/O pin (LAB I/O bank) |
| ピン 6 | I/O — User I/O pin (LAB I/O bank) |
| ピン 7 | I/O — User I/O pin (LAB I/O bank) |
| ピン 8 | I/O — User I/O pin (LAB I/O bank) |
| ピン 9 | I/O — User I/O pin (LAB I/O bank) |
| ピン 10 | I/O — User I/O pin (LAB I/O bank) |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — User I/O pin (LAB I/O bank) |
| ピン 13 | I/O — User I/O pin (LAB I/O bank) |
| ピン 14 | I/O — User I/O pin (LAB I/O bank) |
| ピン 15 | I/O — User I/O pin (LAB I/O bank) |
| ピン 16 | I/O — User I/O pin (LAB I/O bank) |
| ピン 17 | I/O — User I/O pin (LAB I/O bank) |
| ピン 18 | I/O — User I/O pin (LAB I/O bank) |
| ピン 19 | I/O — User I/O pin (LAB I/O bank) |
| ピン 20 | I/O — User I/O pin (LAB I/O bank) |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin (LAB I/O bank) |
| ピン 23 | I/O — User I/O pin (LAB I/O bank) |
| ピン 24 | I/O — User I/O pin (LAB I/O bank) |
| ピン 25 | I/O — User I/O pin (LAB I/O bank) |
| ピン 26 | I/O — User I/O pin (LAB I/O bank) |
| ピン 27 | I/O — User I/O pin (LAB I/O bank) |
| ピン 28 | I/O — User I/O pin (LAB I/O bank) |
| ピン 29 | I/O — User I/O pin (LAB I/O bank) |
| ピン 30 | I/O — User I/O pin (LAB I/O bank) |
| ピン 31 | VCC — 5V supply (VCCIO) |
| ピン 32 | I/O — User I/O pin (LAB I/O bank) |
| ピン 33 | I/O — User I/O pin (LAB I/O bank) |
| ピン 34 | I/O — User I/O pin (LAB I/O bank) |
| ピン 35 | I/O — User I/O pin (LAB I/O bank) |
| ピン 36 | I/O — User I/O pin (LAB I/O bank) |
| ピン 37 | I/O — User I/O pin (LAB I/O bank) |
| ピン 38 | I/O — User I/O pin (LAB I/O bank) |
| ピン 39 | I/O — User I/O pin (LAB I/O bank) |
| ピン 40 | I/O — User I/O pin (LAB I/O bank) |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin (LAB I/O bank) |
| ピン 43 | I/O — User I/O pin (LAB I/O bank) |
| ピン 44 | I/O — User I/O pin (LAB I/O bank) |
| ピン 45 | I/O — User I/O pin (LAB I/O bank) |
| ピン 46 | I/O — User I/O pin (LAB I/O bank) |
| ピン 47 | I/O — User I/O pin (LAB I/O bank) |
| ピン 48 | I/O — User I/O pin (LAB I/O bank) |
| ピン 49 | I/O — User I/O pin (LAB I/O bank) |
| ピン 50 | I/O — User I/O pin (LAB I/O bank) |
| ピン 51 | VCC — 5V supply (VCCIO) |
| ピン 52 | I/O — User I/O pin (LAB I/O bank) |
| ピン 53 | I/O — User I/O pin (LAB I/O bank) |
| ピン 54 | I/O — User I/O pin (LAB I/O bank) |
| ピン 55 | I/O — User I/O pin (LAB I/O bank) |
| ピン 56 | I/O — User I/O pin (LAB I/O bank) |
| ピン 57 | I/O — User I/O pin (LAB I/O bank) |
| ピン 58 | I/O — User I/O pin (LAB I/O bank) |
| ピン 59 | I/O — User I/O pin (LAB I/O bank) |
| ピン 60 | I/O — User I/O pin (LAB I/O bank) |
| ピン 61 | GND — Ground |
| ピン 62 | I/O — User I/O pin (LAB I/O bank) |
| ピン 63 | I/O — User I/O pin (LAB I/O bank) |
| ピン 64 | I/O — User I/O pin (LAB I/O bank) |
| ピン 65 | I/O — User I/O pin (LAB I/O bank) |
| ピン 66 | I/O — User I/O pin (LAB I/O bank) |
| ピン 67 | I/O — User I/O pin (LAB I/O bank) |
| ピン 68 | I/O — User I/O pin (LAB I/O bank) |
| ピン 69 | I/O — User I/O pin (LAB I/O bank) |
| ピン 70 | I/O — User I/O pin (LAB I/O bank) |
| ピン 71 | VCC — 5V supply (VCCINT) |
| ピン 72 | I/O — User I/O pin (LAB I/O bank) |
| ピン 73 | I/O — User I/O pin (LAB I/O bank) |
| ピン 74 | I/O — User I/O pin (LAB I/O bank) |
| ピン 75 | I/O — User I/O pin (LAB I/O bank) |
| ピン 76 | I/O — User I/O pin (LAB I/O bank) |
| ピン 77 | I/O — User I/O pin (LAB I/O bank) |
| ピン 78 | I/O — User I/O pin (LAB I/O bank) |
| ピン 79 | I/O — User I/O pin (LAB I/O bank) |
| ピン 80 | I/O — User I/O pin (LAB I/O bank) |
| ピン 81 | GND — Ground |
| ピン 82 | I/O — User I/O pin (LAB I/O bank) |
| ピン 83 | I/O — User I/O pin (LAB I/O bank) |
| ピン 84 | I/O — User I/O pin (LAB I/O bank) |
| ピン 85 | I/O — User I/O pin (LAB I/O bank) |
| ピン 86 | I/O — User I/O pin (LAB I/O bank) |
| ピン 87 | I/O — User I/O pin (LAB I/O bank) |
| ピン 88 | I/O — User I/O pin (LAB I/O bank) |
| ピン 89 | I/O — User I/O pin (LAB I/O bank) |
| ピン 90 | I/O — User I/O pin (LAB I/O bank) |
| ピン 91 | VCC — 5V supply (VCCIO) |
| ピン 92 | I/O — User I/O pin (LAB I/O bank) |
| ピン 93 | I/O — User I/O pin (LAB I/O bank) |
| ピン 94 | I/O — User I/O pin (LAB I/O bank) |
| ピン 95 | I/O — User I/O pin (LAB I/O bank) |
| ピン 96 | I/O — User I/O pin (LAB I/O bank) |
| ピン 97 | I/O — User I/O pin (LAB I/O bank) |
| ピン 98 | I/O — User I/O pin (LAB I/O bank) |
| ピン 99 | I/O — User I/O pin (LAB I/O bank) |
| ピン 100 | I/O — User I/O pin (LAB I/O bank) |
| ピン 101 | GND — Ground |
| ピン 102 | I/O — User I/O pin (LAB I/O bank) |
| ピン 103 | I/O — User I/O pin (LAB I/O bank) |
| ピン 104 | I/O — User I/O pin (LAB I/O bank) |
| ピン 105 | I/O — User I/O pin (LAB I/O bank) |
| ピン 106 | I/O — User I/O pin (LAB I/O bank) |
| ピン 107 | I/O — User I/O pin (LAB I/O bank) |
| ピン 108 | I/O — User I/O pin (LAB I/O bank) |
| ピン 109 | I/O — User I/O pin (LAB I/O bank) |
| ピン 110 | I/O — User I/O pin (LAB I/O bank) |
| ピン 111 | VCC — 5V supply (VCCINT) |
| ピン 112 | I/O — User I/O pin (LAB I/O bank) |
| ピン 113 | I/O — User I/O pin (LAB I/O bank) |
| ピン 114 | I/O — User I/O pin (LAB I/O bank) |
| ピン 115 | I/O — User I/O pin (LAB I/O bank) |
| ピン 116 | I/O — User I/O pin (LAB I/O bank) |
| ピン 117 | I/O — User I/O pin (LAB I/O bank) |
| ピン 118 | I/O — User I/O pin (LAB I/O bank) |
| ピン 119 | I/O — User I/O pin (LAB I/O bank) |
| ピン 120 | I/O — User I/O pin (LAB I/O bank) |
| ピン 121 | GND — Ground |
| ピン 122 | I/O — User I/O pin (LAB I/O bank) |
| ピン 123 | I/O — User I/O pin (LAB I/O bank) |
| ピン 124 | I/O — User I/O pin (LAB I/O bank) |
| ピン 125 | I/O — User I/O pin (LAB I/O bank) |
| ピン 126 | I/O — User I/O pin (LAB I/O bank) |
| ピン 127 | I/O — User I/O pin (LAB I/O bank) |
| ピン 128 | I/O — User I/O pin (LAB I/O bank) |
| ピン 129 | I/O — User I/O pin (LAB I/O bank) |
| ピン 130 | I/O — User I/O pin (LAB I/O bank) |
| ピン 131 | VCC — 5V supply (VCCIO) |
| ピン 132 | I/O — User I/O pin (LAB I/O bank) |
| ピン 133 | I/O — User I/O pin (LAB I/O bank) |
| ピン 134 | I/O — User I/O pin (LAB I/O bank) |
| ピン 135 | I/O — User I/O pin (LAB I/O bank) |
| ピン 136 | I/O — User I/O pin (LAB I/O bank) |
| ピン 137 | I/O — User I/O pin (LAB I/O bank) |
| ピン 138 | I/O — User I/O pin (LAB I/O bank) |
| ピン 139 | I/O — User I/O pin (LAB I/O bank) |
| ピン 140 | I/O — User I/O pin (LAB I/O bank) |
| ピン 141 | GND — Ground |
| ピン 142 | I/O — User I/O pin (LAB I/O bank) |
| ピン 143 | I/O — User I/O pin (LAB I/O bank) |
| ピン 144 | I/O — User I/O pin (LAB I/O bank) |
| ピン 145 | I/O — User I/O pin (LAB I/O bank) |
| ピン 146 | I/O — User I/O pin (LAB I/O bank) |
| ピン 147 | I/O — User I/O pin (LAB I/O bank) |
| ピン 148 | I/O — User I/O pin (LAB I/O bank) |
| ピン 149 | I/O — User I/O pin (LAB I/O bank) |
| ピン 150 | I/O — User I/O pin (LAB I/O bank) |
| ピン 151 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 152 | TMS — JTAG Test Mode Select |
| ピン 153 | TCK — JTAG Test Clock |
| ピン 154 | TDO — JTAG Test Data Out |
| ピン 155 | NC — Not connected (per datasheet) |
| ピン 156 | NC — Not connected (per datasheet) |
| ピン 157 | GND — Ground |
| ピン 158 | OE1 — Output Enable 1 (global) |
| ピン 159 | OE2/GCLK2 — Output Enable 2 / Global Clock 2 |
| ピン 160 | GCLK1 — Global Clock 1 |
主な用途
EPM7192SQI160-10N の用途: 6 件s: Industrial Bus Address Decoding, PCI Bridge Glue Logic, Motor Control Sequencing, Legacy 5V System Glue Logic, Telecom Backplane Buffering, Test & Measurement Front-End.
Industrial Bus Address Decoding
The EPM7192SQI160-10N's 192 macrocells and 124 user I/Os make it well suited to industrial bus address decoding where multiple peripherals share an address-mapped bus such as ISA, PC/104, or legacy VME. The 10 ns pin-to-pin delay guarantees deterministic address-to-chip-select latency, which is critical when a single CPLD must decode dozens of peripheral windows in real time. With EEPROM-based non-volatile configuration, the decoder powers up fully active - no boot ROM is needed and there is no FPGA-style configuration delay that could miss the first bus cycles. Industrial PLC backplanes and process-control cards can drop this part into a PQFP-160 socket and immediately gain reliable address-decoding glue logic.
おすすめ
PCI Bridge Glue Logic
Legacy PCI adapter cards and embedded PCI bridges use the EPM7192SQI160-10N to implement hot-plug control signals, interrupt steering, and arbitration glue. The 124 user I/Os comfortably route the full complement of PCI sideband signals (PERR, SERR, STOP, DEVSEL, TRDY, IRDY) plus local-bus interface signals, while the 10 ns delay meets PCI 33 MHz setup/hold budgets. Its 5V-tolerant I/Os allow direct interfacing with classic 5V PCI slots without external transceivers. The non-volatile EEPROM bitstream lets a PCI card enumerate immediately at power-on without BIOS-side configuration overhead.
おすすめ
Motor Control Sequencing
Stepper and brushless DC motor controllers benefit from the EPM7192SQI160-10N's deterministic state-machine execution and 167 MHz internal counter frequency, which are ideal for generating commutation waveforms, PWM gating signals, and encoder decoding in real time. The 192 macrocells can host multiple parallel state machines - one for each motor axis - while the 124 I/Os drive H-bridge enable lines, current-sense comparators, and Hall-effect sensor inputs without external muxing. The 5V CMOS outputs interface directly to industry-standard gate drivers, eliminating level shifters in 24V industrial motion systems.
おすすめ
Legacy 5V System Glue Logic
The EPM7192SQI160-10N shines in legacy 5V systems - such as industrial controllers, test equipment, and avionics retrofit boards - where replacing discrete 74LS/74F glue with one CPLD reduces board area and improves reliability. Its 5.0V VCCINT and VCCIO rails connect directly to existing 5V power planes, and its 124 I/Os replace dozens of discrete AND/OR gates, latches, and decoder chips. The non-volatile configuration survives brown-out events that would otherwise wipe an SRAM-based FPGA, and JTAG boundary scan supports legacy manufacturing-test infrastructure built around IEEE 1149.1.
おすすめ
Telecom Backplane Buffering
Central-office telecom equipment frequently relies on the EPM7192SQI160-10N as a backplane buffer and protocol-translation device between T1/E1 framers, HDLC controllers, and TDM switching fabrics. The 10 ns propagation delay preserves tight timing margins on backplane traces, while the 5V I/Os drive the long, terminated buses typical of telecom shelves. In-system programmability allows field upgrades over JTAG without removing line cards, and 124 I/Os handle 8-bit parallel TDM buses plus framing and clock-distribution signals without external mux logic.
おすすめ
Test & Measurement Front-End
Bench-top test instruments and ATE (Automatic Test Equipment) fixtures use the EPM7192SQI160-10N to implement pin-electronics drivers, pattern-generation sequencers, and timing-edge generators with deterministic latency. The 10 ns tPD is fast enough for sub-100 MHz digital test patterns, and the 124 I/Os route enough channels to drive a moderate-density test head. JTAG-based ISP lets fixture designers update the test pattern over USB-Blaster or ByteBlaster without disassembling the fixture - critical in production ATE environments.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM7192SQI160-10N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM7192SQI160-10 | EPM7192SQC160-10N | EPM7192SQC160-15 | EPM7192SQC160-7N | EPM7192SQC160-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| User I/Os | 124 | 124 | 124 | 124 | 124 | 124 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 15 ns | 7 ns | 10 ns |
| Internal Frequency | 167 MHz | 167 MHz | 167 MHz | 125 MHz | 175.4 MHz | 167 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to 70C (industrial, 'N') | 0C to 70C (commercial) | 0C to 70C (industrial) | 0C to 70C (commercial) | 0C to 70C (industrial) | 0C to 70C (commercial) |
主な差別化要因
- Highest-density 5V MAX 7000S with 124 user I/Os （vs EPM7192SQC160-10N)
- Same PQFP-160 footprint across the entire MAX 7192 family （vs EPM7192SQC160-15)
- Drop-in speed-grade upgrade path （vs EPM7192SQC160-7N)
設計ノート
The EPM7192SQI160-10N requires a tightly regulated 5.0V supply on VCCINT and VCCIO pins. Place 0.1uF decoupling capacitors as close as practical to each VCC pin and bulk 10uF tantalum or ceramic caps near the package corners. Avoid powering the device from a switching regulator without adequate filtering - the 5V EEPROM charge pump can inject noise into the logic supply and cause ISP programming failures or marginal timing.
The PQFP-160 package has 0.5 mm pitch leads that demand a 4-layer PCB with a solid ground plane directly under the device. Keep high-speed traces on the opposite side and use 0.2 mm / 8 mil trace-and-space for fan-out. Provide a continuous thermal copper pour under the PQFP body (the package is plastic so thermal dissipation is moderate but a copper island reduces junction-to-ambient thermal resistance).
Do not confuse the EPM7192SQI160-10N (industrial 0C-70C, 'N' suffix) with the EPM7192SQI160-10 (commercial). Both are PQFP-160 and pin-compatible, but the device ID differs and existing Quartus / MAX+PLUS II project files targeting the -10 may need recompilation for the -10N silicon. Also verify the JTAG chain order - the EPM7192SQI160-10N TDI/TMS/TCK/TDO pin locations follow the datasheet, and swapping in a faster -7 speed grade without recompiling may change BSDL behavior.
Although the 5V CMOS I/Os are robust, place 22-33 ohm series-termination resistors on clock outputs (GCLK1, GCLK2/OE2) if the trace length exceeds 50 mm to prevent ringing on fast edges. For high-fanout signals (chip selects, OE, GCLK), use a clock-buffer tree rather than a single output driving multiple loads, since the EPM7192SQI160-10N I/O drive strength is specified for moderate loads only.
コンプライアンス情報
RoHS compliance per lead-free PQFP-160 package marking. The part is not AEC-Q100 qualified (industrial grade only). REACH and conflict-minerals compliance per Intel/Altera product environmental reports.
