EPM9560RC240-15YY - MAX 9000 CPLD 560 Macrocells | Intel | 240-RQFP
部品番号: EPM9560RC240-15YY ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $95 | $95.00 |
| 10 | $86.5 | $865.00 |
| 100 | $78 | $7,800.00 |
| 500 | $70.25 | $35,125.00 |
| 1,000 | $64.5 | $64,500.00 |
EPM9560RC240-15YY 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style AND/OR arrays with a central interconnect matrix. Within the broader taxonomy it sits as a sibling to the FPGA (Field-Programmable Gate Array); CPLDs are deterministic, low-power, and pin-for-pin predictable, while FPGAs are LUT-based and higher density. CPLDs belong to the family of programmable logic devices, which themselves are a sub-category of digital semiconductors used for glue logic, bus interfacing, and state-machine replacement.
Key features include in-system programmability via the IEEE 1149.1 (JTAG) interface, a 5.0 V single-supply core, pin-compatible speed-grade options (-10, -12, -15), and MultiVolt I/O supporting mixed 5 V / 3.3 V signalling. The MAX 9000A architecture uses Logic Array Blocks (LABs) tied together by a programmable interconnect array (PIA), providing deterministic 15 ns pin-to-pin timing across all 560 macrocells with no routing-induced jitter.
Typical applications include high-speed glue logic for 32-bit microprocessors, bus arbitration and interface bridging (PCI, ISA, VME), peripheral controllers, and digital state-machine replacement in telecommunications and industrial control. The wide 191-I/O count also suits multi-channel buffer/driver consolidation and large address-decoder functions.
When designing with this device, observe the 5 V VCC requirement and ensure JTAG chain integrity if multiple devices are cascaded. Decoupling requires 0.1 uF ceramic capacitors close to each VCC/GND pair, with a bulk tantalum or ceramic capacitor on each supply plane. Programming uses the IEEE 1149.1 boundary-scan chain and is supported by Altera/Intel Quartus and legacy MAX+PLUS II tools.
This page synthesizes distributor pricing, drop-in same-package alternatives from the MAX 9000 family, and practical design notes not collected in any single manufacturer document.
ドロップイン代替品: EPM9560RC240-15YY — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RC240-15YY （同一形状・フットプリント） — 相違点: Package, Family, Device Type, Operating Temperature, User I/O Pins.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RC240-15
✅ ドロップイン✓ 在庫あり
$174.72 / 個
データシートを見る →EPM9560RC240-15W
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC240-15N
✅ ドロップイン✓ 在庫あり
$27.85 / 個
データシートを見る →EPM9560RC240-15C
✅ ドロップイン✓ 在庫あり
価格はお問い合わせください
データシートを見る →EPM9560RC240-12
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM9560ARC240-10
✅ ドロップイン✓ 在庫あり
$28.8 / 個
データシートを見る →EPM9560RC240-15YY 最大定格＆電気的特性
| Family | MAX 9000A |
| Logic Type | CMOS EEPROM-based CPLD |
| Number of Macrocells | 560 |
| Usable Gates | 12,000 |
| Number of User I/O | 191 |
| Maximum Operating Frequency | 117.6 MHz |
| Propagation Delay (tpd) | 15 ns |
| Supply Voltage (VCC) | 5.0 V |
| Programmability | In-system via IEEE 1149.1 (JTAG) |
| Package Type | RQFP-240 (Plastic Quad Flat Pack) |
| 実装タイプ | Surface Mount |
| 動作温度 | 0 C to +70 C (commercial) |
| Speed Grade | -15 |
| RoHS ステータス | Non-RoHS (YY suffix indicates non-compliant / matte tin or SnPb lead finish per Altera legacy convention) |
EPM9560RC240-15YY rqfp-240 (plastic quad flat pack) ピン配置ガイド
EPM9560RC240-15YY (rqfp-240 (plastic quad flat pack) パッケージ) のピン配置。 このデジタルICには、GPIO、通信インターフェース (UART、SPI、I2C)、および電源ピンが含まれています。代替ピン機能と設定オプションについては、メーカーのデータシートを参照してください。組み込みシステム設計とPCBレイアウトに不可欠です。
詳細なピン配置データはありません: EPM9560RC240-15YY.
詳細は データシート をご参照ください。
主な用途
EPM9560RC240-15YY の用途: 6 件s: 32-bit Microprocessor Glue Logic, PCI / VME Bus Bridge, Industrial Control State Machine, Peripheral Controller Hub, Address Decoder / Chip-Select Generator, Legacy Telecom Line Card.
32-bit Microprocessor Glue Logic
The EPM9560RC240-15YY is well suited for 32-bit microprocessor glue logic because its 560 macrocells and 191 user I/Os deliver enough capacity to consolidate dozens of 74-series decoder, latch, and bus-driver chips into one CPLD. The deterministic 15 ns pin-to-pin propagation delay matches 50-66 MHz system buses without timing-closure issues, and the JTAG (IEEE 1149.1) interface allows in-system reconfiguration. Place the part between the CPU and memory/peripheral bus to consolidate address decoding, wait-state generation, and chip-select logic; expect 60-70% board-area reduction compared to discrete PAL implementations.
おすすめ
PCI / VME Bus Bridge
The EPM9560RC240-15YY serves as a PCI-to-local bus or VME bus bridge because the 191 I/O count and 5 V MultiVolt interface directly drive 32-bit PCI signalling at 33 MHz. Its 560 macrocells hold full PCI target-state machines, parity generation, and interrupt-acknowledge logic in a single device, while the deterministic 15 ns tpd meets PCI 2.1 tVAL timing without wait states. Use the JTAG chain to in-system update bridge firmware; ensure trace impedance of 65 ohms +/- 10% for the PCI segment.
おすすめ
Industrial Control State Machine
The EPM9560RC240-15YY is a strong fit for industrial state-machine controllers due to its 560 macrocells supporting 50-100 states with combinational and registered outputs, plus 191 I/Os for sensor and actuator interfacing. The 5 V core and 0-70 C commercial temperature range suit factory-floor cabinets; for harsher environments use the EPM9560RC240-15C industrial-temperature variant. The deterministic 15 ns tpd eliminates race conditions in sequential logic, a key advantage over microcontrollers with interrupt latency.
おすすめ
Peripheral Controller Hub
The EPM9560RC240-15YY can replace multiple PAL/GAL devices in peripheral hubs (USB, SCSI, IDE) because its 12,000-gate capacity and 191 I/Os allow channel multiplexing, command decoding, and DMA handshaking in a single chip. The 5 V tolerance on every I/O pin interfaces directly with legacy 5 V peripherals without level shifters. Power consumption is approximately 1.5-2 W at full toggle rate; provide at least 4 layer PCB with dedicated ground plane.
おすすめ
Address Decoder / Chip-Select Generator
The EPM9560RC240-15YY excels at large address-decoding tasks (e.g., 32-bit systems needing 20+ chip selects) because each macrocell delivers a product term with up to 36 inputs, far more than discrete 22V10 PALs. The 15 ns tpd means the decoded chip-select arrives well within typical CPU access times. Place the part adjacent to the memory bus to minimize trace delay. The JTAG ISP allows last-minute address-map adjustments without board rework.
おすすめ
Legacy Telecom Line Card
The EPM9560RC240-15YY is commonly found in legacy telecom line cards for T1/E1 framers, HDLC controllers, and time-slot interchangers. Its 560 macrocells consolidate framing, alarm, and switching logic that previously required 8-12 discrete PALs, while 5 V tolerance interfaces directly with telecom ASICs of that era. The 15 ns tpd easily handles 1.544/2.048 MHz TDM buses with margin. Note: for new designs, migrate to MAX V 5M570ZE64 or MAX II EPM240 CPLDs.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RC240-15YY — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RC240-15 | EPM9560RC240-15W | EPM9560RC240-15N | EPM9560RC240-15C | EPM9560RC240-12 | EPM9560ARC240-10 |
|---|---|---|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel | Intel | Intel | Intel |
| Package | RQFP-240 | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| User I/O | 191 | 191 | 191 | 191 | 191 | 191 | 191 |
| Propagation Delay (tpd) | 15 ns | 15 ns | 15 ns | 15 ns | 15 ns | 12 ns (-20%) | 10 ns (-33%) |
| Maximum Frequency | 117.6 MHz | 117.6 MHz | 117.6 MHz | 117.6 MHz | 117.6 MHz | ~147 MHz (+25%) | ~176 MHz (+50%) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| RoHS Compliance | Non-RoHS (YY suffix) | RoHS | RoHS | Pb-free | RoHS (industrial temp) | RoHS | RoHS |
主な差別化要因
- Non-RoHS lead finish variant （vs EPM9560RC240-15)
- 15 ns deterministic tpd across 560 macrocells （vs EPM9560ARC240-10)
- 191 user I/O in RQFP-240 package （vs EPM9560RC208-20)
設計ノート
The EPM9560RC240-15YY requires a clean 5.0 V VCC supply with +/-5% tolerance. Place a 0.1 uF X7R ceramic decoupling capacitor within 5 mm of every VCC/GND pair (24 VCC pins and 24 GND pins on the RQFP-240). Add a single 22 uF tantalum or 47 uF ceramic bulk capacitor near the package center. Estimated: at 50% toggle rate with 191 I/Os, ICC core current is approximately 300-400 mA, so budget 2-2.5 W worst-case dissipation and verify with the actual design toggle activity.
The RQFP-240 package has a 0.5 mm pitch and 32 mm body size; use 4-layer PCB with dedicated ground plane directly beneath the CPLD. All 24 GND pins must be soldered with low-impedance vias to the inner ground plane (at least 2 vias per GND pin). JTAG signals (TDI, TDO, TMS, TCK, TRST) should be routed as a 4-wire chain with 10 kohm pull-ups on TCK/TMS/TDI and a 10 kohm pull-down on TRST to prevent spurious configuration. Reserve a JTAG header even on production boards for in-field ISP.
Do not confuse the EPM9560RC240-15YY (non-RoHS) with the EPM9560RC240-15 (RoHS) - they are pin-compatible but may fail Pb-free reflow profiles if the YY suffix part is used. Also note that the MAX 9000A family is NRND; new designs should migrate to MAX V (5M570ZE64) or MAX II (EPM240) CPLDs, which require Quartus instead of MAX+PLUS II and have different footprints - PCB redesign will be required for the migration.
コンプライアンス情報
YY suffix per Altera legacy ordering convention indicates non-RoHS lead finish (SnPb or matte-tin). Not AEC-Q100 qualified (CPLD, not an automotive-grade part by default). Reach, halogen-free, and conflict-mineral status not stated in available distributor data; marked unknown.
