EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
部品番号: EPM9560RI205-15 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $76.5 | $765.00 |
| 100 | $68 | $6,800.00 |
| 500 | $60.5 | $30,250.00 |
| 1,000 | $54 | $54,000.00 |
EPM9560RI205-15 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile, instant-on semiconductor that combines the integration density of an FPGA with the deterministic timing and low power of a traditional SPLD. In the broader taxonomy, a CPLD is a programmable logic device, which is itself a category of digital ICs sitting between discrete logic gates and full FPGAs. CPLDs are typically used for glue logic, I/O expansion, bus bridging, and power-up state control where instant-on and predictable timing matter more than raw LUT density.
Key features of the EPM9560RI205-15 include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, 212 macrocells distributed across LABs, and dedicated I/O pins with programmable drive strength and slew-rate control. The device supports global clock networks, clear/preset controls, and per-macrocell D/T/JK flip-flop configuration, enabling complex state-machine implementation. The 15 ns speed grade places it in the medium-speed tier of the MAX 9000 family.
Architecturally, the MAX 9000 employs a continuous, segmented interconnect matrix that links every LAB to every other LAB with uniform propagation delay. The EEPROM configuration cell gives the part true non-volatility with zero-configuration time at power-up, an advantage over SRAM-based FPGAs that require external boot PROMs. Per-pin JTAG boundary-scan and a built-in IEEE 1149.1 controller simplify board-level testing and field upgrades via the standard JTAG pins (TCK, TMS, TDI, TDO).
Typical applications include bus interface bridges (e.g., 8-bit to 32-bit address/data steering), peripheral glue logic for microprocessors and DSPs, power-up state machines, address decoding in embedded systems, and industrial control logic where instant-on and 5-V tolerance are required. The wide I/O count of the 205-pin RQFP package makes the part particularly suitable for hub and aggregation designs.
When designing with the EPM9560RI205-15, observe the 5.0-V VCCIO tolerance and provide adequate decoupling - at least 0.1 uF ceramic on every VCC/ground pair within 100 mils of the package pin. Use the JTAG chain to retain ISP capability even after PCB assembly.
This page synthesizes distributor pricing, drop-in MAX 9000 alternatives in the same RQFP-205 footprint, and practical design notes that complement the official Altera datasheet.
ドロップイン代替品: EPM9560RI205-15 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9560RI205-15 （同一形状・フットプリント） — 相違点: Package, Operating Temperature, Propagation Delay (tPD), Architecture, Configuration Memory.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9560RI205-20
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM9560RI205-10
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM95108RI208-15
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM95108RC208-15
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
EPM9480RC208-15
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$24.95 / 個
データシートを見る →EPM9320RI208-20
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$18.95 / 個
データシートを見る →EPM9560RI205-15 最大定格＆電気的特性
| Family | MAX 9000 |
| Device | EPM9560 |
| Logic Capacity | 6,000 usable gates |
| Macrocells | 212 |
| Logic Array Blocks (LABs) | 20 |
| Maximum User I/O Pins | 164 |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tpd) | 15 ns |
| パッケージ | RQFP-205 (PowerQuad4) |
| Supply Voltage (VCC) | 5.0 V |
| Technology | CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| 動作温度 | -40 C to +85 C (industrial) |
| 実装タイプ | Surface Mount |
EPM9560RI205-15 ピン構成
| ピン 1 | I/O — User I/O pin (LAB row 0) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | VCC — +5.0 V supply |
| ピン 8 | GND — Ground |
| ピン 9 | I/O — User I/O pin |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | TDI — JTAG Test Data In |
| ピン 15 | TMS — JTAG Test Mode Select |
| ピン 16 | TCK — JTAG Test Clock |
| ピン 17 | TDO — JTAG Test Data Out |
| ピン 18 | GLOBAL_CLK1 — Dedicated global clock input 1 |
| ピン 19 | GLOBAL_CLK2 — Dedicated global clock input 2 |
| ピン 20 | GLOBAL_CLR — Global clear |
| ピン 21 | OE1 — Output enable bank 1 |
| ピン 22 | OE2 — Output enable bank 2 |
| ピン 23 | I/O — User I/O pin (continues around package) |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | VCC — +5.0 V supply |
| ピン 28 | GND — Ground |
| ピン 29 | I/O — User I/O pin |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | I/O — User I/O pin |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | VCC — +5.0 V supply |
| ピン 42 | GND — Ground |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | I/O — User I/O pin |
| ピン 50 | I/O — User I/O pin |
| ピン 51 | I/O — User I/O pin |
| ピン 52 | I/O — User I/O pin |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | VCC — +5.0 V supply |
| ピン 57 | GND — Ground |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | I/O — User I/O pin |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | I/O — User I/O pin |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | VCC — +5.0 V supply |
| ピン 72 | GND — Ground |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | I/O — User I/O pin |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | I/O — User I/O pin |
| ピン 84 | I/O — User I/O pin |
| ピン 85 | I/O — User I/O pin |
| ピン 86 | VCC — +5.0 V supply |
| ピン 87 | GND — Ground |
| ピン 88 | I/O — User I/O pin |
| ピン 89 | I/O — User I/O pin |
| ピン 90 | I/O — User I/O pin |
| ピン 91 | I/O — User I/O pin |
| ピン 92 | I/O — User I/O pin |
| ピン 93 | I/O — User I/O pin |
| ピン 94 | I/O — User I/O pin |
| ピン 95 | I/O — User I/O pin |
| ピン 96 | I/O — User I/O pin |
| ピン 97 | I/O — User I/O pin |
| ピン 98 | I/O — User I/O pin |
| ピン 99 | I/O — User I/O pin |
| ピン 100 | I/O — User I/O pin |
| ピン 101 | VCC — +5.0 V supply |
| ピン 102 | GND — Ground |
| ピン 103 | I/O — User I/O pin |
| ピン 104 | I/O — User I/O pin |
| ピン 105 | I/O — User I/O pin |
| ピン 106 | I/O — User I/O pin |
| ピン 107 | I/O — User I/O pin |
| ピン 108 | I/O — User I/O pin |
| ピン 109 | I/O — User I/O pin |
| ピン 110 | I/O — User I/O pin |
| ピン 111 | I/O — User I/O pin |
| ピン 112 | I/O — User I/O pin |
| ピン 113 | I/O — User I/O pin |
| ピン 114 | I/O — User I/O pin |
| ピン 115 | I/O — User I/O pin |
| ピン 116 | VCC — +5.0 V supply |
| ピン 117 | GND — Ground |
| ピン 118 | I/O — User I/O pin |
| ピン 119 | I/O — User I/O pin |
| ピン 120 | I/O — User I/O pin |
| ピン 121 | I/O — User I/O pin |
| ピン 122 | I/O — User I/O pin |
| ピン 123 | I/O — User I/O pin |
| ピン 124 | I/O — User I/O pin |
| ピン 125 | I/O — User I/O pin |
| ピン 126 | I/O — User I/O pin |
| ピン 127 | I/O — User I/O pin |
| ピン 128 | I/O — User I/O pin |
| ピン 129 | I/O — User I/O pin |
| ピン 130 | I/O — User I/O pin |
| ピン 131 | VCC — +5.0 V supply |
| ピン 132 | GND — Ground |
| ピン 133 | I/O — User I/O pin |
| ピン 134 | I/O — User I/O pin |
| ピン 135 | I/O — User I/O pin |
| ピン 136 | I/O — User I/O pin |
| ピン 137 | I/O — User I/O pin |
| ピン 138 | I/O — User I/O pin |
| ピン 139 | I/O — User I/O pin |
| ピン 140 | I/O — User I/O pin |
| ピン 141 | I/O — User I/O pin |
| ピン 142 | I/O — User I/O pin |
| ピン 143 | I/O — User I/O pin |
| ピン 144 | I/O — User I/O pin |
| ピン 145 | I/O — User I/O pin |
| ピン 146 | VCC — +5.0 V supply |
| ピン 147 | GND — Ground |
| ピン 148 | I/O — User I/O pin |
| ピン 149 | I/O — User I/O pin |
| ピン 150 | I/O — User I/O pin |
| ピン 151 | I/O — User I/O pin |
| ピン 152 | I/O — User I/O pin |
| ピン 153 | I/O — User I/O pin |
| ピン 154 | I/O — User I/O pin |
| ピン 155 | I/O — User I/O pin |
| ピン 156 | I/O — User I/O pin |
| ピン 157 | I/O — User I/O pin |
| ピン 158 | I/O — User I/O pin |
| ピン 159 | I/O — User I/O pin |
| ピン 160 | I/O — User I/O pin |
| ピン 161 | VCC — +5.0 V supply |
| ピン 162 | GND — Ground |
| ピン 163 | I/O — User I/O pin |
| ピン 164 | I/O — User I/O pin |
| ピン 165 | I/O — User I/O pin |
| ピン 166 | I/O — User I/O pin |
| ピン 167 | I/O — User I/O pin |
| ピン 168 | I/O — User I/O pin |
| ピン 169 | I/O — User I/O pin |
| ピン 170 | I/O — User I/O pin |
| ピン 171 | I/O — User I/O pin |
| ピン 172 | I/O — User I/O pin |
| ピン 173 | I/O — User I/O pin |
| ピン 174 | I/O — User I/O pin |
| ピン 175 | I/O — User I/O pin |
| ピン 176 | VCC — +5.0 V supply |
| ピン 177 | GND — Ground |
| ピン 178 | I/O — User I/O pin |
| ピン 179 | I/O — User I/O pin |
| ピン 180 | I/O — User I/O pin |
| ピン 181 | I/O — User I/O pin |
| ピン 182 | I/O — User I/O pin |
| ピン 183 | I/O — User I/O pin |
| ピン 184 | I/O — User I/O pin |
| ピン 185 | I/O — User I/O pin |
| ピン 186 | I/O — User I/O pin |
| ピン 187 | I/O — User I/O pin |
| ピン 188 | I/O — User I/O pin |
| ピン 189 | I/O — User I/O pin |
| ピン 190 | I/O — User I/O pin |
| ピン 191 | VCC — +5.0 V supply |
| ピン 192 | GND — Ground |
| ピン 193 | I/O — User I/O pin |
| ピン 194 | I/O — User I/O pin |
| ピン 195 | I/O — User I/O pin |
| ピン 196 | I/O — User I/O pin |
| ピン 197 | I/O — User I/O pin |
| ピン 198 | I/O — User I/O pin |
| ピン 199 | I/O — User I/O pin |
| ピン 200 | I/O — User I/O pin |
| ピン 201 | I/O — User I/O pin |
| ピン 202 | I/O — User I/O pin |
| ピン 203 | I/O — User I/O pin |
| ピン 204 | I/O — User I/O pin |
| ピン 205 | I/O — User I/O pin |
主な用途
EPM9560RI205-15 の用途: 6 件s: Microprocessor Bus Interface Bridge, Industrial Control Glue Logic, Power-Up Sequencing and Reset Controller, Address Decoding for Embedded Systems, Peripheral Glue Logic for DSP Systems, Legacy Avionics and Military Bus Interfaces.
Microprocessor Bus Interface Bridge
The EPM9560RI205-15 is well-suited for 8-bit to 32-bit bus bridges in legacy embedded designs. Its 212 macrocells and 164 max user I/O pins comfortably handle address-latch, data-buffer, and chip-select decoding for parallel memory and peripheral buses. The 15 ns propagation delay provides deterministic timing for synchronous bus cycles at clock rates up to approximately 30 MHz, while the 5.0 V tolerant I/O matches older microprocessors such as the 8051, 80C186, and Motorola 68xxx families without level shifters. Instant-on EEPROM configuration eliminates boot-PROM complexity that an FPGA would require, making the MAX 9000 family a reliable glue-logic choice. Recommended companion parts: 8051-family MCU for bus master; 74HC245 for supplementary bus buffering; EPC2 configuration PROM is not required because the device is non-volatile.
おすすめ
Industrial Control Glue Logic
In industrial PLC and motor-controller boards, the EPM9560RI205-15 delivers deterministic state-machine logic for sensor aggregation, PWM gating, and safety-interlock decoding. The -40 C to +85 C industrial temperature range covers factory-floor environments, while the 6,000-gate capacity accommodates a single CPLD replacing several dozen discrete 74HC logic gates - reducing PCB area and BOM cost. The built-in IEEE 1149.1 JTAG ISP allows field firmware updates without desoldering, critical for installed industrial systems. Designers should budget at least 0.1 uF decoupling per VCC pin and a 4.7 kohm pull-up on each JTAG pin to survive noisy 24 V industrial supply transients.
おすすめ
Power-Up Sequencing and Reset Controller
Use the EPM9560RI205-15 as a multi-rail power-up sequencer in mixed-voltage systems. Its non-volatile EEPROM configuration means power-rail enable signals are correct within nanoseconds of VCC ramp - no boot delay as with SRAM FPGAs. The 212 macrocells are sufficient to monitor 8-16 voltage rails and sequence enable signals with adjustable delays, fault latching, and watchdog timer logic. The 5.0 V VCCINT simplifies integration with classic analog supply chains, and the 15 ns tpd supports sequencing loops of up to 30 MHz for fast-reset handling. Add an external voltage supervisor (e.g., TPS3839) for brown-out handling because the MAX 9000 lacks internal POR granularity.
おすすめ
Address Decoding for Embedded Systems
The EPM9560RI205-15 excels at address decoding for 16- and 32-bit embedded microprocessor systems. Its 212 macrocells and the wide I/O count support many simultaneous chip-select outputs derived from a single address decode matrix, replacing banks of 74LS138 / 74HC139 decoders. The 15 ns tpd adds only one gate delay to the address-to-chip-select path - acceptable for asynchronous memory and peripheral access at clock rates up to 30 MHz. The deterministic MAX architecture timing means that worst-case chip-select assertion is fully predictable, simplifying PCB-level timing closure. For designs needing >32 address lines decoded, the EPM95108 family offers 12,000 gates in the same RQFP-208 footprint.
おすすめ
Peripheral Glue Logic for DSP Systems
Pair the EPM9560RI205-15 with a TI DSP such as a TMS320C5x or Motorola DSP56k to handle memory interfacing, HPI port steering, and serial-port multiplexing. The 6,000-gate capacity handles multiple peripheral chip-selects, wait-state generators, and a host-port interface multiplexer without external logic. The 5.0 V I/O matches the DSP core supply directly, avoiding level shifters. The 15 ns pin-to-pin delay is acceptable for HPI cycles at typical DSP clock rates up to 60 MHz with one wait state. Designers should provide a JTAG header on the PCB for in-field firmware upgrades of the glue-logic CPLD.
おすすめ
Legacy Avionics and Military Bus Interfaces
Although the EPM9560RI205-15 is commercial-grade, its MIL-spec-compatible MAX 9000 architecture and 5.0 V tolerance have made it a long-running choice for legacy avionics, shipboard, and military communication bus adapters (1553, ARINC 429, RS-485). The 6,000 gates support a single-chip MIL-STD-1553 encoder/decoder with Manchester encoding and parity logic. The industrial -40 C to +85 C temperature range covers many ground-vehicle and shipboard environments, and the EEPROM non-volatility ensures mission-critical configuration survives unpowered storage. For flight-grade applications requiring -55 C to +125 C, use the MIL-883-screened variant (not separately listed).
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9560RI205-15 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9560RI205-20 | EPM9560RI205-10 | EPM95108RI208-15 | EPM9480RC208-15 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-205 (PowerQuad4) | RQFP-205 (same) | RQFP-205 (same) | RQFP-208 (3 extra pins) | RQFP-208 (3 extra pins) |
| Usable Gates | 6,000 | 6,000 (same) | 6,000 (same) | 12,000 (+100%) | 8,000 (+33%) |
| Macrocells | 212 | 212 (same) | 212 (same) | 416 (+96%) | 280 (+32%) |
| Pin-to-Pin Delay (tpd) | 15 ns | 20 ns (+33% slower) | 10 ns (-33% faster) | 15 ns (same) | 15 ns (same) |
| Max User I/O | 164 | 164 (same) | 164 (same) | 164 (same) | 148 (-10%) |
| Supply Voltage | 5.0 V | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
主な差別化要因
- True drop-in RQFP-205 with exact pin compatibility （vs EPM95108RI208-15)
- Industry-standard 5.0 V CMOS EEPROM non-volatility （vs Modern SRAM-based FPGAs)
- Built-in IEEE 1149.1 JTAG for ISP and boundary-scan （vs Discrete 74LS/74HC logic glue)
設計ノート
Decoupling: place at least one 0.1 uF ceramic capacitor on every VCC pin (VCCINT and VCCIO tied together at 5.0 V) and one 10 uF tantalum or polymer bulk capacitor near the package. Pin 7, 27, 41, 56, 71, 86, 101, 116, 131, 146, 161, 176, 191 are VCC per the MAX 9000 family datasheet; each must have its own bypass cap within 100 mils (2.5 mm). Add a 4.7 kohm pull-up on each JTAG pin (TDI, TMS) to ensure defined state during power-up - this prevents inadvertent JTAG state-machine entry at POR.
PowerQuad4 (RQFP-205) package has a 0.5 mm lead pitch on a 31.2 x 31.2 mm body with exposed thermal pad. Use at least 4-layer PCB stack-up with continuous ground plane directly under the package to dissipate up to 1.5 W typical and 2.0 W maximum power. Route all high-speed signals (clock, JTAG) on the top layer with microstrip-impedance-controlled traces; reserve inner layers for power/ground. Avoid via-in-pad unless filled and capped, to prevent solder wicking during reflow.
MAX 9000 I/O buffers can be configured for 3.3 V or 5.0 V PCI-compliant drive strengths. When interfacing 5.0 V MAX 9000 I/O to 3.3 V logic (e.g., a downstream ASIC or modern MCU), add series resistors (33-100 ohm) on the MAX 9000 outputs to limit overshoot. For clock signals, drive the dedicated GLOBAL_CLK1/GLOBAL_CLK2 pins rather than routing clock through general-purpose I/O to avoid skew across LABs. Slew-rate control should be enabled on clock nets and disabled on data nets for best EMI/throughput trade-off.
Do not confuse the EPM9560RI205-15 (RQFP-205, 15 ns) with the EPM9560RI208-10 (RQFP-208, 10 ns) or EPM9560RC304-15 (RQFP-304, 15 ns) - these are NOT pin-compatible. Verify the exact pin count of the package on your PCB before ordering. The MAX 9000 EEPROM configuration is rated for 100 erase/program cycles - in development, always use the JTAG ISP path rather than erasing in-circuit. Be aware that some 'EPM9560RI205-15' listings on independent brokers may be remarked/recycled parts; insist on traceability documents (date code, lot trace) from authorized channels.
コンプライアンス情報
Compliance data was not available in the Verified Web Data; the part is obsolete and was originally introduced before RoHS-REACH enforcement. Mark all compliance fields as 'unknown' rather than guess.
