EPM9560RI205-15 - MAX 9000 CPLD, 6K Gates, 15ns | Altera
MPN: EPM9560RI205-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $76.5 | $765.00 |
| 100 | $68 | $6,800.00 |
| 500 | $60.5 | $30,250.00 |
| 1,000 | $54 | $54,000.00 |
Drop-in alternatives for EPM9560RI205-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RI205-20
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9560RI205-10
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM95108RI208-15
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM95108RC208-15
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9480RC208-15
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$24.95 / Unit
View Datasheet βEPM9320RI208-20
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$18.95 / Unit
View Datasheet βEPM9560RI205-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device | EPM9560 |
| Logic Capacity | 6,000 usable gates |
| Macrocells | 212 |
| Logic Array Blocks (LABs) | 20 |
| Maximum User I/O Pins | 164 |
| Speed Grade | -15 (15 ns pin-to-pin delay) |
| Propagation Delay (tpd) | 15 ns |
| Package | RQFP-205 (PowerQuad4) |
| Supply Voltage (VCC) | 5.0 V |
| Technology | CMOS EEPROM |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount |
EPM9560RI205-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (LAB row 0) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | VCC β +5.0 V supply |
| Pin 8 | GND β Ground |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | TDO β JTAG Test Data Out |
| Pin 18 | GLOBAL_CLK1 β Dedicated global clock input 1 |
| Pin 19 | GLOBAL_CLK2 β Dedicated global clock input 2 |
| Pin 20 | GLOBAL_CLR β Global clear |
| Pin 21 | OE1 β Output enable bank 1 |
| Pin 22 | OE2 β Output enable bank 2 |
| Pin 23 | I/O β User I/O pin (continues around package) |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | VCC β +5.0 V supply |
| Pin 28 | GND β Ground |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | VCC β +5.0 V supply |
| Pin 42 | GND β Ground |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | VCC β +5.0 V supply |
| Pin 57 | GND β Ground |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | VCC β +5.0 V supply |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | VCC β +5.0 V supply |
| Pin 87 | GND β Ground |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | I/O β User I/O pin |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | VCC β +5.0 V supply |
| Pin 102 | GND β Ground |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | I/O β User I/O pin |
| Pin 107 | I/O β User I/O pin |
| Pin 108 | I/O β User I/O pin |
| Pin 109 | I/O β User I/O pin |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | I/O β User I/O pin |
| Pin 116 | VCC β +5.0 V supply |
| Pin 117 | GND β Ground |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | I/O β User I/O pin |
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| Pin 127 | I/O β User I/O pin |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | VCC β +5.0 V supply |
| Pin 132 | GND β Ground |
| Pin 133 | I/O β User I/O pin |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | I/O β User I/O pin |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | I/O β User I/O pin |
| Pin 146 | VCC β +5.0 V supply |
| Pin 147 | GND β Ground |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | I/O β User I/O pin |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | I/O β User I/O pin |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | VCC β +5.0 V supply |
| Pin 162 | GND β Ground |
| Pin 163 | I/O β User I/O pin |
| Pin 164 | I/O β User I/O pin |
| Pin 165 | I/O β User I/O pin |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | I/O β User I/O pin |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | I/O β User I/O pin |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | I/O β User I/O pin |
| Pin 176 | VCC β +5.0 V supply |
| Pin 177 | GND β Ground |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | I/O β User I/O pin |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | I/O β User I/O pin |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | I/O β User I/O pin |
| Pin 184 | I/O β User I/O pin |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | I/O β User I/O pin |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | I/O β User I/O pin |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | VCC β +5.0 V supply |
| Pin 192 | GND β Ground |
| Pin 193 | I/O β User I/O pin |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | I/O β User I/O pin |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | I/O β User I/O pin |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | I/O β User I/O pin |
| Pin 204 | I/O β User I/O pin |
| Pin 205 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RI205-15 is suitable for 6 applications: Microprocessor Bus Interface Bridge, Industrial Control Glue Logic, Power-Up Sequencing and Reset Controller, Address Decoding for Embedded Systems, Peripheral Glue Logic for DSP Systems, Legacy Avionics and Military Bus Interfaces.
Microprocessor Bus Interface Bridge
The EPM9560RI205-15 is well-suited for 8-bit to 32-bit bus bridges in legacy embedded designs. Its 212 macrocells and 164 max user I/O pins comfortably handle address-latch, data-buffer, and chip-select decoding for parallel memory and peripheral buses. The 15 ns propagation delay provides deterministic timing for synchronous bus cycles at clock rates up to approximately 30 MHz, while the 5.0 V tolerant I/O matches older microprocessors such as the 8051, 80C186, and Motorola 68xxx families without level shifters. Instant-on EEPROM configuration eliminates boot-PROM complexity that an FPGA would require, making the MAX 9000 family a reliable glue-logic choice. Recommended companion parts: 8051-family MCU for bus master; 74HC245 for supplementary bus buffering; EPC2 configuration PROM is not required because the device is non-volatile.
Recommended
Industrial Control Glue Logic
In industrial PLC and motor-controller boards, the EPM9560RI205-15 delivers deterministic state-machine logic for sensor aggregation, PWM gating, and safety-interlock decoding. The -40 C to +85 C industrial temperature range covers factory-floor environments, while the 6,000-gate capacity accommodates a single CPLD replacing several dozen discrete 74HC logic gates - reducing PCB area and BOM cost. The built-in IEEE 1149.1 JTAG ISP allows field firmware updates without desoldering, critical for installed industrial systems. Designers should budget at least 0.1 uF decoupling per VCC pin and a 4.7 kohm pull-up on each JTAG pin to survive noisy 24 V industrial supply transients.
Recommended
Power-Up Sequencing and Reset Controller
Use the EPM9560RI205-15 as a multi-rail power-up sequencer in mixed-voltage systems. Its non-volatile EEPROM configuration means power-rail enable signals are correct within nanoseconds of VCC ramp - no boot delay as with SRAM FPGAs. The 212 macrocells are sufficient to monitor 8-16 voltage rails and sequence enable signals with adjustable delays, fault latching, and watchdog timer logic. The 5.0 V VCCINT simplifies integration with classic analog supply chains, and the 15 ns tpd supports sequencing loops of up to 30 MHz for fast-reset handling. Add an external voltage supervisor (e.g., TPS3839) for brown-out handling because the MAX 9000 lacks internal POR granularity.
Recommended
Address Decoding for Embedded Systems
The EPM9560RI205-15 excels at address decoding for 16- and 32-bit embedded microprocessor systems. Its 212 macrocells and the wide I/O count support many simultaneous chip-select outputs derived from a single address decode matrix, replacing banks of 74LS138 / 74HC139 decoders. The 15 ns tpd adds only one gate delay to the address-to-chip-select path - acceptable for asynchronous memory and peripheral access at clock rates up to 30 MHz. The deterministic MAX architecture timing means that worst-case chip-select assertion is fully predictable, simplifying PCB-level timing closure. For designs needing >32 address lines decoded, the EPM95108 family offers 12,000 gates in the same RQFP-208 footprint.
Recommended
Peripheral Glue Logic for DSP Systems
Pair the EPM9560RI205-15 with a TI DSP such as a TMS320C5x or Motorola DSP56k to handle memory interfacing, HPI port steering, and serial-port multiplexing. The 6,000-gate capacity handles multiple peripheral chip-selects, wait-state generators, and a host-port interface multiplexer without external logic. The 5.0 V I/O matches the DSP core supply directly, avoiding level shifters. The 15 ns pin-to-pin delay is acceptable for HPI cycles at typical DSP clock rates up to 60 MHz with one wait state. Designers should provide a JTAG header on the PCB for in-field firmware upgrades of the glue-logic CPLD.
Recommended
Legacy Avionics and Military Bus Interfaces
Although the EPM9560RI205-15 is commercial-grade, its MIL-spec-compatible MAX 9000 architecture and 5.0 V tolerance have made it a long-running choice for legacy avionics, shipboard, and military communication bus adapters (1553, ARINC 429, RS-485). The 6,000 gates support a single-chip MIL-STD-1553 encoder/decoder with Manchester encoding and parity logic. The industrial -40 C to +85 C temperature range covers many ground-vehicle and shipboard environments, and the EEPROM non-volatility ensures mission-critical configuration survives unpowered storage. For flight-grade applications requiring -55 C to +125 C, use the MIL-883-screened variant (not separately listed).
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RI205-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RI205-20 | EPM9560RI205-10 | EPM95108RI208-15 | EPM9480RC208-15 |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | RQFP-205 (PowerQuad4) | RQFP-205 (same) | RQFP-205 (same) | RQFP-208 (3 extra pins) | RQFP-208 (3 extra pins) |
| Usable Gates | 6,000 | 6,000 (same) | 6,000 (same) | 12,000 (+100%) | 8,000 (+33%) |
| Macrocells | 212 | 212 (same) | 212 (same) | 416 (+96%) | 280 (+32%) |
| Pin-to-Pin Delay (tpd) | 15 ns | 20 ns (+33% slower) | 10 ns (-33% faster) | 15 ns (same) | 15 ns (same) |
| Max User I/O | 164 | 164 (same) | 164 (same) | 164 (same) | 148 (-10%) |
| Supply Voltage | 5.0 V | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| JTAG ISP | Yes (IEEE 1149.1) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
Key Differentiators
- True drop-in RQFP-205 with exact pin compatibility (vs EPM95108RI208-15)
- Industry-standard 5.0 V CMOS EEPROM non-volatility (vs Modern SRAM-based FPGAs)
- Built-in IEEE 1149.1 JTAG for ISP and boundary-scan (vs Discrete 74LS/74HC logic glue)
Design Notes
Decoupling: place at least one 0.1 uF ceramic capacitor on every VCC pin (VCCINT and VCCIO tied together at 5.0 V) and one 10 uF tantalum or polymer bulk capacitor near the package. Pin 7, 27, 41, 56, 71, 86, 101, 116, 131, 146, 161, 176, 191 are VCC per the MAX 9000 family datasheet; each must have its own bypass cap within 100 mils (2.5 mm). Add a 4.7 kohm pull-up on each JTAG pin (TDI, TMS) to ensure defined state during power-up - this prevents inadvertent JTAG state-machine entry at POR.
PowerQuad4 (RQFP-205) package has a 0.5 mm lead pitch on a 31.2 x 31.2 mm body with exposed thermal pad. Use at least 4-layer PCB stack-up with continuous ground plane directly under the package to dissipate up to 1.5 W typical and 2.0 W maximum power. Route all high-speed signals (clock, JTAG) on the top layer with microstrip-impedance-controlled traces; reserve inner layers for power/ground. Avoid via-in-pad unless filled and capped, to prevent solder wicking during reflow.
MAX 9000 I/O buffers can be configured for 3.3 V or 5.0 V PCI-compliant drive strengths. When interfacing 5.0 V MAX 9000 I/O to 3.3 V logic (e.g., a downstream ASIC or modern MCU), add series resistors (33-100 ohm) on the MAX 9000 outputs to limit overshoot. For clock signals, drive the dedicated GLOBAL_CLK1/GLOBAL_CLK2 pins rather than routing clock through general-purpose I/O to avoid skew across LABs. Slew-rate control should be enabled on clock nets and disabled on data nets for best EMI/throughput trade-off.
Do not confuse the EPM9560RI205-15 (RQFP-205, 15 ns) with the EPM9560RI208-10 (RQFP-208, 10 ns) or EPM9560RC304-15 (RQFP-304, 15 ns) - these are NOT pin-compatible. Verify the exact pin count of the package on your PCB before ordering. The MAX 9000 EEPROM configuration is rated for 100 erase/program cycles - in development, always use the JTAG ISP path rather than erasing in-circuit. Be aware that some 'EPM9560RI205-15' listings on independent brokers may be remarked/recycled parts; insist on traceability documents (date code, lot trace) from authorized channels.
Compliance Information
Compliance data was not available in the Verified Web Data; the part is obsolete and was originally introduced before RoHS-REACH enforcement. Mark all compliance fields as 'unknown' rather than guess.
