LTC2143IUP-12 - 12-Bit 80Msps Dual ADC, 64-QFN | Analog Devices
部品番号: LTC2143IUP-12 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $45.5 | $45.50 |
| 10 | $41.2 | $412.00 |
| 100 | $37.46 | $3,746.00 |
| 500 | $35.8 | $17,900.00 |
| 1,000 | $33.1 | $33,100.00 |
LTC2143IUP-12 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that converts real-world analog waveforms into discrete digital codes for processing, storage, or transmission. The pipelined ADC architecture — of which the LTC2143IUP-12 is an instance — uses multiple low-resolution stages (typically 1.5 bits/stage) with inter-stage residue amplifiers to achieve high sampling rates at moderate resolution. Pipelined ADCs sit within the broader hierarchy: ADC → data converter → mixed-signal IC → semiconductor. They are the workhorse choice for communications, imaging, and test-and-measurement systems that require multi-MHz input bandwidth and 10-14 bits of resolution.
The LTC2143IUP-12 supports input bandwidths up to approximately 750 MHz, allowing it to under-sample IF signals in communications receivers. Internal voltage reference, programmable digital output timing, and flexible LVDS/CMOS output modes simplify board-level integration. The dual, matched channels eliminate skew between ADC paths in MIMO or diversity receivers, while per-channel gain and offset adjustment registers help correct channel-to-channel mismatches at the system level.
The 1.8 V single-supply architecture plus low power (about 100 mW per channel at 80 Msps) makes the LTC2143IUP-12 well suited for portable and thermally-constrained instrumentation. Optional LVDS outputs minimize digital switching noise on the board, which is critical when the analog inputs are at the millivolt level. Programmable full-scale input range (1 Vpp or 2 Vpp differential) gives designers headroom when interfacing with a variety of front-end amplifiers and anti-alias filters.
Typical applications include cellular base-station receivers, software-defined radio (SDR) platforms, medical imaging front ends, portable test and measurement equipment, and multi-channel data acquisition systems. The wide input bandwidth also suits digital oscilloscopes and spectrum analyzer front ends.
When designing with the LTC2143IUP-12, place the analog input traces as 100-ohm differential pairs with a grounded coplanar-waveguide structure, and keep the exposed pad soldered to a continuous ground plane for thermal dissipation and low-impedance return. Use the internal reference by default and decouple AVDD/DVDD/OVRDV with 0.1 uF and 10 uF ceramic capacitors as close to the pins as possible.
This page synthesizes DigiKey and Mouser stock/pricing, drop-in pin-compatible alternatives in the same 64-QFN footprint, and practical design notes drawn from the Analog Devices datasheet — information that you will not find on any single distributor page.
ドロップイン代替品: LTC2143IUP-12 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2143IUP-12 （同一形状・フットプリント） — 相違点: Package, Resolution, SFDR, SNR, Operating Temperature Range.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2144IUP-12
✅ ドロップイン✓ 在庫あり
$47.2 / 個
データシートを見る →LTC2145IUP-12
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2143CUP-12
✅ ドロップイン✓ 在庫あり
$22.1 / 個
データシートを見る →LTC2142IUP-14
✅ ドロップイン✓ 在庫あり
$34.71 / 個
データシートを見る →LTC2143IUP-12 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate | 80 Msps |
| Number of Channels | 2 (simultaneous sampling) |
| Architecture | Pipelined |
| Input Type | Differential |
| 電源電圧 | 1.8 V (single) |
| Power Dissipation | approximately 100 mW per channel at 80 Msps |
| SNR | 70.6 dB |
| SFDR | 89 dB |
| Full-Scale Input Range | 1 Vpp or 2 Vpp differential (programmable) |
| Digital Output | LVDS or CMOS (parallel, programmable) |
| 動作温度 | -40C to +85C (industrial) |
| パッケージ | 64-QFN (UP, 9x9 mm) with exposed pad |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant (PBF suffix) |
| Internal Reference | Yes |
LTC2143IUP-12 ピン構成
| ピン 1 | GND — Ground reference |
| ピン 2 | AIN1+ — Channel 1 differential analog input (positive) |
| ピン 3 | AIN1- — Channel 1 differential analog input (negative) |
| ピン 4 | VCM1 — Channel 1 common-mode voltage |
| ピン 5 | GND — Ground reference |
| ピン 6 | AIN2+ — Channel 2 differential analog input (positive) |
| ピン 7 | AIN2- — Channel 2 differential analog input (negative) |
| ピン 8 | VCM2 — Channel 2 common-mode voltage |
| ピン 9 | REF — Internal reference decoupling / external reference input |
| ピン 10 | REFT — Top reference decoupling |
| ピン 11 | REFB — Bottom reference decoupling |
| ピン 12 | GND — Ground reference |
| ピン 13 | AVDD — 1.8V analog supply |
| ピン 14 | GND — Ground reference |
| ピン 15 | AVDD — 1.8V analog supply |
| ピン 16 | SENSE — Reference programming pin |
| ピン 17 | OGND — Output driver ground |
| ピン 18 | OVDD — Output driver supply |
| ピン 19 | PAR/SER — Parallel/Serial programming mode select |
| ピン 20 | CS — Chip select (serial mode) |
| ピン 21 | SCK — Serial interface clock / output mode control |
| ピン 22 | SDI — Serial data input |
| ピン 23 | SDO — Serial data output |
| ピン 24 | RESET — Reset / power-down control |
| ピン 25 | NC — Not connected (per datasheet) |
| ピン 26 | D0_1 — Channel 1 data output bit 0 (LSB) |
| ピン 27 | D1_1 — Channel 1 data output bit 1 |
| ピン 28 | D2_1 — Channel 1 data output bit 2 |
| ピン 29 | D3_1 — Channel 1 data output bit 3 |
| ピン 30 | D4_1 — Channel 1 data output bit 4 |
| ピン 31 | D5_1 — Channel 1 data output bit 5 |
| ピン 32 | D6_1 — Channel 1 data output bit 6 |
| ピン 33 | D7_1 — Channel 1 data output bit 7 |
| ピン 34 | D8_1 — Channel 1 data output bit 8 |
| ピン 35 | D9_1 — Channel 1 data output bit 9 |
| ピン 36 | D10_1 — Channel 1 data output bit 10 |
| ピン 37 | D11_1 — Channel 1 data output bit 11 (MSB) |
| ピン 38 | D0_2 — Channel 2 data output bit 0 (LSB) |
| ピン 39 | D1_2 — Channel 2 data output bit 1 |
| ピン 40 | D2_2 — Channel 2 data output bit 2 |
| ピン 41 | D3_2 — Channel 2 data output bit 3 |
| ピン 42 | D4_2 — Channel 2 data output bit 4 |
| ピン 43 | D5_2 — Channel 2 data output bit 5 |
| ピン 44 | D6_2 — Channel 2 data output bit 6 |
| ピン 45 | D7_2 — Channel 2 data output bit 7 |
| ピン 46 | D8_2 — Channel 2 data output bit 8 |
| ピン 47 | D9_2 — Channel 2 data output bit 9 |
| ピン 48 | D10_2 — Channel 2 data output bit 10 |
| ピン 49 | D11_2 — Channel 2 data output bit 11 (MSB) |
| ピン 50 | OGND — Output driver ground |
| ピン 51 | OVDD — Output driver supply |
| ピン 52 | CLK+ — Differential clock input (positive) |
| ピン 53 | CLK- — Differential clock input (negative) |
| ピン 54 | GND — Ground reference |
| ピン 55 | DVDD — 1.8V digital supply |
| ピン 56 | GND — Ground reference |
| ピン 57 | DRO_1 — Channel 1 data ready output |
| ピン 58 | DRO_2 — Channel 2 data ready output |
| ピン 59 | NC — Not connected (per datasheet) |
| ピン 60 | GND — Ground reference |
| ピン 61 | AVDD — 1.8V analog supply |
| ピン 62 | GND — Ground reference |
| ピン 63 | AVDD — 1.8V analog supply |
| ピン 64 | GND — Ground reference |
主な用途
LTC2143IUP-12 の用途: 6 件s: Cellular Base-Station Receiver IF Sampling, Software-Defined Radio (SDR) Platform, Medical Imaging Front End, Portable Test & Measurement Instrumentation, Multi-Channel Data Acquisition Systems, Digital Oscilloscope / Spectrum Analyzer Front End.
Cellular Base-Station Receiver IF Sampling
The LTC2143IUP-12's 70.6 dB SNR and 89 dB SFDR at 80 Msps are well matched to cellular base-station receivers where dual-channel IF-sampling removes the need for a second downconversion stage. Per the 21454312fa datasheet, the wide input bandwidth allows direct sampling of IF frequencies up to several hundred MHz, eliminating analog mixers. The 1.8 V single supply simplifies the power tree, and the 64-QFN exposed pad provides low thermal resistance on the base-station PCB. Place the dual ADCs in front of a digital downconverter for diversity/MIMO receiver paths; differential analog inputs reject common-mode noise from the RF front end.
おすすめ
Software-Defined Radio (SDR) Platform
SDR platforms benefit from the LTC2143IUP-12's dual simultaneous-sampling channels, which capture I/Q baseband or a wideband IF in a single IC. The 12-bit resolution gives roughly 70 dB dynamic range — adequate for many SDR use cases from HF through L-band — while 80 Msps handles bandwidths up to ~40 MHz per channel. Per the 21454312fa datasheet, the programmable LVDS outputs ease routing into FPGAs (e.g., Xilinx or Altera) that perform the digital downconversion. Differential analog inputs pair naturally with common SDR front-end amplifiers and anti-alias filters.
おすすめ
Medical Imaging Front End
Ultrasound and other medical imaging front ends require simultaneous multi-channel sampling with low noise — a perfect fit for the LTC2143IUP-12. Per the 21454312fa datasheet, the 70.6 dB SNR preserves the dynamic range needed for low-amplitude echo signals, while the dual channel lets designers cascade multiple ICs for 4/8/16-channel beamformer arrays. The 1.8 V supply keeps per-channel power around 10 mW (lowered by clock-rate scaling), important for portable cart-based ultrasound. Industrial temperature rating (-40C to +85C) supports clinical and field-deployed equipment.
おすすめ
Portable Test & Measurement Instrumentation
Handheld oscilloscopes, spectrum analyzers, and data-acquisition modules need a compact, low-power, dual-channel ADC like the LTC2143IUP-12. The 1.8 V single supply and ~100 mW per channel dissipation per the 21454312fa datasheet enable battery-powered designs without exotic thermal management. The 80 Msps sample rate (160 Msps interleaved) covers audio, vibration, and general-purpose sensor digitisation. Differential inputs reject ground noise from cable harnesses, while the exposed-pad QFN keeps the analog front end thermally isolated from the FPGA/processor.
おすすめ
Multi-Channel Data Acquisition Systems
Industrial data-acquisition cards needing simultaneous sampling on many channels benefit from cascading LTC2143IUP-12 devices — for example, 4 ICs deliver 8 channels with shared clocking per the 21454312fa datasheet. The 64-QFN footprint is small enough for high-density PCI/PCIe/PXI cards. 12-bit resolution is sufficient for vibration monitoring, condition-based maintenance, and process control. Programmable 1 Vpp or 2 Vpp full-scale inputs let designers match a wide range of sensor outputs (IEPE accelerometers, strain gauges, RTD bridges).
おすすめ
Digital Oscilloscope / Spectrum Analyzer Front End
Entry-level and mid-range oscilloscopes use the LTC2143IUP-12 in time-interleaved configurations for effective sample rates up to 160 Msps across two channels, with matched gain/offset registers per the 21454312fa datasheet. Wide input bandwidth supports direct digitisation of signals up to ~50 MHz without a front-end downconverter. LVDS output mode minimizes digital switching noise that could couple back into the analog front end via the ground plane — a common pitfall in dense scope designs. Pin-compatible upgrade to LTC2144IUP-12 (105 Msps) or LTC2145IUP-12 (125 Msps) lets OEMs reuse one PCB across product tiers.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2143IUP-12 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2144IUP-12 | LTC2145IUP-12 | LTC2143CUP-12 | LTC2142IUP-14 |
|---|---|---|---|---|---|
| Package | 64-QFN (UP, 9x9 mm) | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same | 64-QFN (UP, 9x9 mm) - same |
| Brand | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 14 bits |
| Channels | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 2 (simultaneous sampling) | 1 |
| Supply Voltage | 1.8 V (single) | 1.8 V (single) | 1.8 V (single) | 1.8 V (single) | 1.8 V (single) |
| Temperature Range | -40C to +85C (industrial) | -40C to +85C | -40C to +85C | 0C to +70C (commercial) | -40C to +85C |
| Digital Output | LVDS or CMOS (parallel, programmable) | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS | LVDS or CMOS |
主な差別化要因
- Higher sample rate option in same footprint （vs LTC2144IUP-12)
- Industrial temperature range vs commercial-grade pricing （vs LTC2143CUP-12)
- 12-bit optimized vs 14-bit higher-resolution alternative （vs LTC2142IUP-14)
- Single 1.8 V supply simplifies power tree （vs AD9268XCPZ-125)
設計ノート
Per the 21454312fa datasheet, the analog inputs (AIN1+/AIN1-, AIN2+/AIN2-) must be routed as 100-ohm differential microstrip or coplanar-waveguide pairs with a continuous ground reference underneath. Keep input traces short, symmetrical, and away from digital outputs (D0_1..D11_2) and clock lines (CLK+/CLK-). Place 0.1 uF and 10 uF ceramic decoupling capacitors as close as possible to each AVDD/DVDD/OVDD pin, with the exposed pad soldered to a continuous, low-impedance ground plane to minimize thermal resistance and provide the analog/digital return path.
Use LVDS output mode for high-density or noisy boards — LVDS differential signaling minimizes ground bounce and switching noise coupling back into the analog front end. If CMOS outputs are required for a low-channel-count design, series-terminate each output with a 33-ohm resistor close to the IC to dampen reflections. Route the clock (CLK+/CLK-) as a differential pair from a low-jitter source (e.g., an AD9517 or equivalent) and avoid crossing clock lines with data outputs to preserve SNR/SFDR per the datasheet's 70.6 dB / 89 dB figures.
Common pitfalls include: (1) failing to solder the exposed pad to ground, which causes thermal runaway and degraded SNR; (2) routing the analog inputs as single-ended (this part requires differential drive); (3) omitting the VCM bypass capacitor on each channel, which reduces CMRR; and (4) driving the analog input beyond the 1 Vpp or 2 Vpp full-scale range, which causes hard clipping and potential long-term damage. Per the datasheet, the SENSE pin must be tied to AVDD for internal reference or to VCM for an external reference — miswiring this pin changes the input full-scale range.
At 80 Msps with both channels active, the LTC2143IUP-12 dissipates approximately 200 mW total (about 100 mW per channel per the 21454312fa datasheet). The 64-QFN exposed pad provides a low thermal-resistance path (~25 C/W theta_JC) — solder the pad to a copper pour of at least 1 square inch to keep junction temperature rise under 5C above ambient. For cascaded multi-IC designs (e.g., 8-channel data acquisition), space the LTC2143IUP-12 devices at least 10 mm apart on the PCB to avoid localized heating.
コンプライアンス情報
RoHS-compliant per DigiKey/Mouser part detail (PBF suffix). Not AEC-Q100 qualified — choose an AEC-Q100-qualified ADC for vehicle applications. The non-PBF variant LTC2143IUP-12 may have different compliance status; order the #PBF suffix for RoHS-compliant designs. Industrial temperature grade only - not military/aerospace qualified.
