SI5335B-B10210-GM - 4-Output Any-Frequency Clock Generator | Skyworks
部品番号: SI5335B-B10210-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.64 | $14.64 |
| 10 | $13.5 | $135.00 |
| 100 | $11.25 | $1,125.00 |
| 500 | $9.85 | $4,925.00 |
| 1,000 | $8.5 | $8,500.00 |
SI5335B-B10210-GM 概要
A clock generator is a clock/timing IC that derives one or more output frequencies from a single reference source. Clock generators integrate a phase-locked loop (PLL) and frequency dividers so that multiple independent clocks can be produced from a common reference, eliminating the need for multiple crystals across a board. Within the broader timing taxonomy, clock generators sit alongside clock buffers, PLL frequency synthesizers, and oscillators as one of four major timing-IC families; the SI5335 specifically targets applications where multiple unrelated clock frequencies are needed and absolute frequency accuracy is critical.
Key features of the SI5335B-B10210-GM include support for any output frequency under 200 MHz, any output format (LVDS, LVPECL, HCSL, CMOS, SSTL), independent 1.5/1.8/2.5/3.3 V output bank supplies, and I2C/SPI programmable output skew and format. The MultiSynth architecture eliminates jitter degradation when fractional frequency conversions are performed, unlike traditional PLL-plus-divider implementations. A built-in crystal input stage accepts an external reference crystal, and the device supports multiple reference inputs and automatic switching for redundancy.
Typical applications include multi-rate telecom line cards, FPGA/ASIC reference clocking, broadcast video equipment, industrial timing backplanes, networking switches/routers, and any high-density board replacing multiple crystals with a single programmable generator. The independent output bank supplies allow direct connection to ASICs with mixed-voltage I/O without level translation.
When designing with this part, treat the order code as fixed for the lifecycle of the design - the SI5335B is factory-customized rather than user-reprogrammable at runtime, so the output configuration must be specified up front using the Skyworks ClockBuilder Pro tool. Decoupling must be placed on every bank supply pin to meet the output jitter specification.
ドロップイン代替品: SI5335B-B10210-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5335B-B10210-GM （同一形状・フットプリント） — 相違点: Number of Outputs, Output Frequency Range, Package, MSL Level, Configuration Interface.
クイック比較ツール — 並列比較する代替部品を選択:
SI5335B-B03900-GMR
✅ ドロップイン✓ 在庫あり
$3.48 / 個
データシートを見る →SI5335B-B10210-GMR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335A-B10210-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335B-B10210-GM 仕様
| Product Type | Clock Generator |
| 出力数 | 4 independent banks |
| Output Frequency Range | 1 MHz to 200 MHz per output |
| Frequency Synthesis Accuracy | 0 ppm |
| Output Formats | LVDS, LVPECL, HCSL, CMOS, SSTL |
| Output Bank Supplies | 1.5 V / 1.8 V / 2.5 V / 3.3 V independent |
| Core Supply Voltage | 1.8 V / 2.5 V / 3.3 V |
| Reference Input | External crystal or clock |
| Configuration Interface | I2C / SPI |
| Architecture | MultiSynth fractional divider |
| パッケージ | 24-pin QFN |
| 実装タイプ | Surface Mount |
| MSLレベル | 2 (1 year) |
| RoHS ステータス | Compliant |
| 動作温度 | -40C to +85C (industrial) |
SI5335B-B10210-GM ピン構成
| ピン 1 | GND — Ground |
| ピン 2 | IN0 — Reference clock input 0 |
| ピン 3 | IN1 — Reference clock input 1 |
| ピン 4 | VDD — Core supply voltage |
| ピン 5 | VDD0A — Output bank 0A supply |
| ピン 6 | OUT0A_P — Output 0A positive (LVDS/LVPECL) |
| ピン 7 | OUT0A_N — Output 0A negative (LVDS/LVPECL) |
| ピン 8 | VDD0B — Output bank 0B supply |
| ピン 9 | OUT0B — Output 0B CMOS / SSTL |
| ピン 10 | VDD1A — Output bank 1A supply |
| ピン 11 | OUT1A_P — Output 1A positive (LVDS/LVPECL) |
| ピン 12 | OUT1A_N — Output 1A negative (LVDS/LVPECL) |
| ピン 13 | VDD1B — Output bank 1B supply |
| ピン 14 | OUT1B — Output 1B CMOS / SSTL |
| ピン 15 | VDD2A — Output bank 2A supply |
| ピン 16 | OUT2A_P — Output 2A positive (LVDS/LVPECL) |
| ピン 17 | OUT2A_N — Output 2A negative (LVDS/LVPECL) |
| ピン 18 | VDD2B — Output bank 2B supply |
| ピン 19 | OUT2B — Output 2B CMOS / SSTL |
| ピン 20 | SDA — I2C data / SPI data |
| ピン 21 | SCL — I2C clock / SPI clock |
| ピン 22 | CSB — Chip select for SPI mode |
| ピン 23 | RST — Reset, active low |
| ピン 24 | VDD — Core supply voltage |
主な用途
SI5335B-B10210-GM の用途: 7 件s: Multi-Rate Telecom Line Card Clocking, FPGA/ASIC Reference Clock Generation, Broadcast Video Equipment Timing, Industrial Control / Automation Backplane, Server / Datacenter Board Clocking, Test & Measurement Instrumentation, Networking Switch / Router Reference Clocking.
Multi-Rate Telecom Line Card Clocking
The SI5335B-B10210-GM is well-suited to telecom line cards needing four non-integer-related clocks for framer, PHY, and switch fabric ASICs. Its MultiSynth fractional divider delivers 0 ppm synthesis accuracy and its independent bank supplies connect directly to 1.8 V and 2.5 V ASIC rails without level translation, saving board real-estate.
おすすめ
FPGA/ASIC Reference Clock Generation
FPGA designs typically need unrelated clocks for transceiver, fabric, and serializer-deserializer blocks. The SI5335B-B10210-GM outputs up to four independent clocks up to 200 MHz, with LVDS/LVPECL/HCSL formats to drive modern FPGA SerDes reference inputs, replacing up to four crystals and reducing BOM cost.
おすすめ
Broadcast Video Equipment Timing
Broadcast switchers and SDI routers need 27 MHz video clocks, 148.5 MHz HD-SDI clocks, and a separate processing-clock reference. The SI5335B-B10210-GM generates all four simultaneously with 0 ppm accuracy, supports CMOS and LVDS outputs to drive typical SDI serializers, and provides per-bank voltage selection for mixed I/O domains.
おすすめ
Industrial Control / Automation Backplane
Industrial backplanes need reliable, mixed-voltage clocks for deterministic Ethernet PHYs, SoC, FPGA, and isolated galvanic transceivers. The SI5335B-B10210-GM provides those clocks from one factory-customized part, supports -40C to +85C industrial operation, and replaces multiple crystals that would otherwise complicate EMC and BOM management in industrial environments.
おすすめ
Server / Datacenter Board Clocking
Server motherboards carry clocks for PCIe, SATA, BMC, and network controllers that are not integer-related. The SI5335B-B10210-GM supplies four such clocks with sub-ps jitter thanks to MultiSynth, supports 100 MHz PCIe Gen3 and 1 GbE reference rates, and helps simplify board layout by consolidating multiple crystals into a single 24-pin QFN.
おすすめ
Test & Measurement Instrumentation
Test instruments often need stable, unrelated clocks for ADC, FPGA, trigger logic, and communication PHYs. The SI5335B-B10210-GM generates those four clocks with 0 ppm synthesis accuracy from a single reference, eliminating frequency drift across the instrument and ensuring calibration stability over time and temperature.
おすすめ
Networking Switch / Router Reference Clocking
Multi-port managed switches and routers carry unrelated clocks for PHY, MAC, control plane CPU, and serialization-deserialization. The SI5335B-B10210-GM supports this in a single chip with four flexible banks and supports I2C/SPI configuration for run-time customization, making it ideal for managed Ethernet switches with multiple port speeds.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5335B-B10210-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5335B-B03900-GMR | SI5335B-B10210-GMR | SI5335A-B10210-GM |
|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 24-pin QFN | 24-pin QFN - same | 24-pin QFN - same | 24-pin QFN - same |
| Number of Outputs | 4 banks | 4 banks | 4 banks | 4 banks |
| Max Output Frequency | 200 MHz | 200 MHz | 200 MHz | 167 MHz |
| Frequency Accuracy | 0 ppm | 0 ppm | 0 ppm | 0 ppm |
| Architecture | MultiSynth fractional divider | MultiSynth | MultiSynth | MultiSynth |
| Order Code / Frequency Plan | B10210 | B03900 | B10210 | B10210 (A-series) |
| Operating Temperature | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
主な差別化要因
- Factory-customized order code with MultiSynth 0 ppm accuracy （vs Discrete crystal oscillators)
- Higher output frequency range with consistent MultiSynth architecture （vs SI5335A-B10210-GM)
- Built-in flexible output formats and per-bank supply voltages （vs SI5338A)
設計ノート
Place a 0.1 uF ceramic decoupling capacitor within 2 mm of every VDD and per-bank supply pin. A bulk 10 uF tantalum or ceramic on each supply rail is recommended to suppress MultiSynth switching noise. The exposed pad must be soldered to a continuous ground plane stitch below the QFN footprint.
Route the LVDS/LVPECL output pairs as 100 ohm differential traces with matched length. Keep CMOS outputs on a different layer or further away from differential pairs to avoid crosstalk. The crystal trace from the crystal to the IC reference pins should be short and guarded by a ground hatch to avoid stray capacitance. MultiSynth architecture produces very low jitter, but output skew drifts with output format and load - account for that in timing budget.
Estimated: The SI5335B is factory-customized by order code (B10210), so the register map and frequency plan are fixed at ordering time. Do not attempt to reconfigure at runtime via I2C - use SI5338 if reconfigurability is needed. Confirm the desired frequency plan in ClockBuilder Pro before ordering; lead times can be longer than stock crystals and re-orders may need new MPN codes. Always reference the Skyworks datasheet to confirm the latest pinout, as some early QFN variants differ.
コンプライアンス情報
RoHS compliant per Skyworks product page listing. Not AEC-Q100 qualified (clock generators typically are not automotive qualified - consult factory for -Q1 variants). MSL 2 per IPC/JEDEC J-STD-020.
