SI5335C-B-GM - 4-Output Any-Freq Clock Generator (<350 MHz) | Skyworks
部品番号: SI5335C-B-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $8.5 | $8.50 |
| 10 | $7.65 | $76.50 |
| 100 | $6.2 | $620.00 |
| 500 | $5.4 | $2,700.00 |
| 1,000 | $4.75 | $4,750.00 |
SI5335C-B-GM 概要
A clock generator (also called a frequency synthesizer or clock generator IC) is a timing IC that produces one or more reference-grade output clocks from a single input reference, replacing multiple crystal oscillators and reducing BOM cost in systems that previously required separate XOs for each frequency. Modern quad clock generators with MultiSynth fractional dividers extend this concept by allowing all four outputs to run on independent, non-integer-related frequencies, eliminating frequency-planning restrictions at the architecture stage.
Key features of the Si5335C family include a frequency range of 1 MHz to 350 MHz per output, sub-200 fs RMS phase jitter (12 kHz to 20 MHz), four independent MultiSynth fractional divider blocks, and five user-defined pins (3, 5, 6, 12, 19) selectable via the ClockBuilder utility. The 24-pin QFN package has a small 4x4 mm footprint and supports storage temperatures from -65 °C to +150 °C.
Internally the Si5335C uses a PLL locked to a 2.5–50 MHz external reference, followed by Skyworks' patented MultiSynth fractional-N divider architecture that provides 0 ppm frequency synthesis error on every output independently. Per-bank supply pins (3.3 V, 2.5 V, 1.8 V, 1.5 V) mean each output bank can drive a different logic level without level translators, simplifying multi-format designs.
Typical applications include telecom and networking line cards, multi-rate Ethernet PHYs, FPGA and processor reference clocks, PCIe Gen 2/3 reference generation, and broadcast video equipment where multiple unrelated frequencies must coexist. Per the manufacturer, the part is supplied in an industrial temperature grade.
When designing in the Si5335C, drive the device with a clean external crystal or CMOS reference and use Skyworks' ClockBuilder desktop utility to generate the per-order factory-programmed NVM image before submitting your unique B-suffix code. Per the datasheet, output format, output enable polarity, and I²C address are configured via the B-code, not by external strapping.
This page synthesizes distributor pricing, drop-in B-code ordering variants, and practical ClockBuilder workflow notes that supplement the manufacturer datasheet.
ドロップイン代替品: SI5335C-B-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5335C-B-GM （同一形状・フットプリント） — 相違点: Number of Outputs, Output Frequency Range, Package, Core Supply Voltage, MSL Level.
クイック比較ツール — 並列比較する代替部品を選択:
SI5335C-B07520-GM
✅ ドロップイン✓ 在庫あり
$4.05 / 個
データシートを見る →SI5335C-B08232-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335C-B07094-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335C-B04635-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5335B-B10210-GM
✅ ドロップイン✓ 在庫あり
$8.5 / 個
データシートを見る →SI5335B-B03900-GMR
✅ ドロップイン✓ 在庫あり
$3.48 / 個
データシートを見る →SI5335C-B-GM 仕様
| Product Type | Clock Generator (Quad, Any-Frequency) |
| 出力数 | 4 (4 banks; differential pair or 2x single-ended per bank) |
| Output Frequency Range | 1 MHz to 350 MHz per output |
| Reference Input Frequency | 2.5 MHz to 50 MHz |
| Number of MultiSynth Dividers | 4 (independent, fractional-N) |
| Output Formats Supported | LVPECL, LVDS, HCSL, LVCMOS, SSTL |
| Output Supply Voltages | 3.3 V, 2.5 V, 1.8 V, 1.5 V (per-bank independent) |
| Core Supply Voltage | 3.3 V, 2.5 V, or 1.8 V |
| Configuration Method | Factory NVM via ClockBuilder (B-suffix code) |
| User-Defined Pins | 5 (pins 3, 5, 6, 12, 19; input/control selectable via ClockBuilder) |
| パッケージ | 24-pin QFN (4x4 mm) |
| Storage Temperature Range | -65 °C to +150 °C |
| ピン数 | 24 |
| Lead-Free / RoHS | Lead-free, RoHS compliant (GM suffix) |
| Family | Si5335 / Si5335C (Web-Customizable Any-Freq Quad Clock Generator) |
SI5335C-B-GM ピン構成
| ピン 1 | GND — Ground |
| ピン 2 | XA — Crystal reference input |
| ピン 3 | USER1 — User-defined pin (ClockBuilder-programmable: input or control function) |
| ピン 4 | IN1 — Input reference 1 (CMOS/XO) |
| ピン 5 | USER2 — User-defined pin (ClockBuilder-programmable) |
| ピン 6 | USER3 — User-defined pin (ClockBuilder-programmable) |
| ピン 7 | OEB — Output enable (active low, per B-code configurable) |
| ピン 8 | VDD — Core supply (3.3 V / 2.5 V / 1.8 V) |
| ピン 9 | VDDO0 — Output bank 0 supply (3.3 / 2.5 / 1.8 / 1.5 V) |
| ピン 10 | CLK0+ — Output bank 0 positive |
| ピン 11 | CLK0- — Output bank 0 negative (or second CMOS) |
| ピン 12 | USER4 — User-defined pin (ClockBuilder-programmable) |
| ピン 13 | VDDO1 — Output bank 1 supply |
| ピン 14 | CLK1+ — Output bank 1 positive |
| ピン 15 | CLK1- — Output bank 1 negative (or second CMOS) |
| ピン 16 | GNDO1 — Ground for output bank 1 |
| ピン 17 | VDDO2 — Output bank 2 supply |
| ピン 18 | CLK2+ — Output bank 2 positive |
| ピン 19 | USER5 — User-defined pin (ClockBuilder-programmable) |
| ピン 20 | CLK2- — Output bank 2 negative (or second CMOS) |
| ピン 21 | VDDO3 — Output bank 3 supply |
| ピン 22 | CLK3+ — Output bank 3 positive |
| ピン 23 | CLK3- — Output bank 3 negative (or second CMOS) |
| ピン 24 | SDA — I²C / SMBus data (per B-code programmable address) |
主な用途
SI5335C-B-GM の用途: 6 件s: Multi-Rate Ethernet PHY Clocking, FPGA Reference & Logic Clock Tree, Telecom Line Card Timing, PCIe Gen 2/3 Reference Generation, Broadcast Video & Image Processing, Industrial Automation & Control.
Multi-Rate Ethernet PHY Clocking
The SI5335C-B-GM's 1 MHz to 350 MHz per-output range and sub-200 fs RMS jitter make it well suited for supplying reference clocks to multi-rate Ethernet PHYs that switch between 1G, 10G, and 25G rates. Four independent MultiSynth fractional dividers let one SI5335C replace four separate crystal oscillators on a line card, each output running at the precise rate the PHY needs without cross-coupling jitter. Independent per-bank supplies (3.3 V/2.5 V/1.8 V/1.5 V) allow the same device to drive an SGMII PHY at 1.8 V LVCMOS while driving a 10G PHY at 2.5 V LVDS, eliminating level translators and reducing board area. Designers should request a custom B-code via ClockBuilder so all four frequencies are factory NVM-locked, ensuring long-term reproducibility across builds.
おすすめ
FPGA Reference & Logic Clock Tree
The SI5335C-B-GM is a strong fit for FPGA designs that demand multiple unrelated logic clocks (e.g., 100 MHz for fabric, 156.25 MHz for transceiver refclk, 50 MHz for DDR, 25 MHz for housekeeping). With four MultiSynth fractional outputs and 0 ppm synthesis error per the datasheet, the device provides four jitter-clean clocks from one external crystal, freeing the FPGA's internal PLLs for dynamic on-die reconfiguration. The 24-pin 4x4 mm QFN lands cleanly on a small fanout region close to the FPGA clock pins, minimizing trace length and matching requirements. Designers should verify ClockBuilder frequency selection supports the FPGA's PLL input frequency range before committing to a B-code.
おすすめ
Telecom Line Card Timing
Telecom line cards frequently need up to four related clocks (BITS reference, TDM bus, Ethernet PHY, and frame pulse) generated from a single Stratum-3/3E input. The SI5335C-B-GM accepts a 2.5-50 MHz reference and produces four independently synthesized outputs up to 350 MHz with per-bank supply flexibility, simplifying mixed LVCMOS and LVPECL fanout. Jitter performance in the low-200 fs range helps the part meet the wander/jitter masks in ITU-T G.813 and G.8261. Industrial temperature grade (the -GM suffix) matches outdoor and central-office thermal environments. Use the ClockBuilder utility to lock all four frequencies into the device NVM before ordering production B-codes.
おすすめ
PCIe Gen 2/3 Reference Generation
PCIe Gen 2 (100 MHz HCSL) and Gen 3 (100 MHz HCSL) endpoints and root complexes require 100 MHz HCSL refclk with sub-300 fs RMS jitter typical, and the SI5335C-B-GM's MultiSynth fractional divider cleanly synthesizes 100 MHz from a reference with phase-noise floor that meets PCIe CEM 3.0 jitter budgets per the Skyworks datasheet. Four outputs allow a single SI5335C to clock a PCIe switch plus its downstream endpoints from one device, simplifying BOM and PCB. HCSL output format is factory-selectable per the ClockBuilder B-code, so no external HCSL driver is required. Output-bank supply must be set to 3.3 V for HCSL swing, which is supported on the Si5335C per-bank supply pins.
おすすめ
Broadcast Video & Image Processing
Broadcast video routers, frame synchronizers, and image-processing pipelines often combine several unrelated pixel clocks (e.g., 74.25 MHz 720p, 148.5 MHz 1080p, 27 MHz reference for SD-SDI, and 74.25 MHz for HD-SDI). The SI5335C-B-GM's any-frequency, any-output capability replaces a stack of separate XOs with one factory-programmed clock generator, shrinking layout area and reducing the number of mechanical crystals that need crystal-pull auditing. Per the datasheet, each of the four outputs delivers 0 ppm error and LVCMOS/LVDS drive flexibility, supporting both SDI serializers and CMOS video processors from the same device. Industrial-grade (-GM) operation supports rack and chassis thermal envelopes.
おすすめ
Industrial Automation & Control
Industrial controllers combine deterministic micro-controller clocks with Ethernet, EtherCAT, or Profinet clocks that need precise but different frequencies. The SI5335C-B-GM delivers four independently synthesized outputs up to 350 MHz from a single reference, which lets engineers consolidate separate oscillators for the MCU, the fieldbus MAC, the supervisory EEPROM, and an Ethernet PHY into a single Skyworks device. Industrial-grade -GM operation from -40 °C to +85 °C (per the family datasheet) supports factory-floor and outdoor cabinet environments. Per the datasheet, the factory-programmed NVM ensures field-deployed units behave identically to bench prototypes, simplifying certification and long-term production control.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5335C-B-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5335C-B07520-GM | SI5335C-B08232-GM | SI5335B-B10210-GM |
|---|---|---|---|---|
| Brand | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions | Skyworks Solutions |
| Package | 24-pin QFN (4x4 mm) | 24-pin QFN (4x4 mm) - same | 24-pin QFN (4x4 mm) - same | 24-pin QFN (4x4 mm) - same |
| Number of Outputs | 4 (any freq 1 MHz to 350 MHz) | 4 (same) | 4 (same) | 4 (same) |
| Output Format Support | LVPECL/LVDS/HCSL/LVCMOS/SSTL (full) | Full (per B-code) | Full (per B-code) | Reduced (no SSTL, no 1.5 V bank) |
| Configuration Method | Factory NVM via ClockBuilder (-B code) | Factory NVM (B-code) | Factory NVM (B-code) | Factory NVM (B-code) |
| Output Supply Voltages | 3.3/2.5/1.8/1.5 V (per-bank) | Same | Same | 3.3/2.5/1.8 V only (no 1.5 V) |
| Parametric Match to SI5335C-B-GM | 100% | 100% (same family, pre-programmed B-code) | 100% (same family, pre-programmed B-code) | ~80% (narrower format/voltage) |
| Typical Unit Price (qty 1) | $8.50 | Varies by distributor; similar to SI5335C family | Similar to SI5335C family | Typically similar / lower |
主な差別化要因
- 5 user-defined, ClockBuilder-programmable I/O pins （vs SI5335B-B10210-GM)
- Per-bank independent output supply including 1.5 V support （vs SI5335B-B10210-GM)
- Full output-format support including SSTL （vs SI5335B-B10210-GM)
設計ノート
Use a single solid ground plane under the 24-pin QFN and stitch vias around the perimeter of the exposed pad. Per the Skyworks datasheet, the exposed pad is the primary thermal path and must be soldered to a 4x4 mm copper island with at least 4 thermal vias tying to inner ground layers. Place crystal/reference traces as short and symmetrical as possible to avoid asymmetric duty-cycle distortion at the input. Keep the output traces length-matched to within 5 mm when using differential LVPECL/LVDS/HCSL outputs to preserve skew.
Do not assume the SI5335C-B-GM is pin-strappable. Every Si5335C requires a customer-specific B-code (a 5-digit suffix) generated from the ClockBuilder utility; the part ships with that exact NVM image and is not field-reprogrammable for frequency. Ordering -B-GM without specifying the B-code yields a factory-default NVM image. Also do not drive the user-defined pins (3, 5, 6, 12, 19) until you confirm their function in the B-code configuration - their direction and polarity varies by B-code, per the datasheet.
Estimated: driving the SI5335C with a CMOS reference between 2.5 MHz and 50 MHz yields the cleanest divider math because the MultiSynth fractional engine has the largest σ-delta margin in this band. For differential output banks (LVPECL / LVDS / HCSL), terminate each output with the appropriate network per the Skyworks application note (LVPECL: 150 Ω Thevenin to VDD-2 V; LVDS: 100 Ω differential; HCSL: 33 Ω series to 50 Ω shunt to GND). Receiving ends must preserve the required common-mode voltage; do not AC-couple HCSL outputs that drive PCIe silicon without a DC bias restoration network.
コンプライアンス情報
-GM suffix denotes lead-free, RoHS-compliant package per Skyworks datasheet. Not AEC-Q100 qualified - request extended automotive options from Skyworks for AEC-Q100 needs.
