SI5345A-D04594-GM - 10-Output Jitter Attenuator | Skyworks
部品番号: SI5345A-D04594-GM ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $35.2 | $352.00 |
| 100 | $31.8 | $3,180.00 |
| 500 | $28.5 | $14,250.00 |
| 1,000 | $25.9 | $25,900.00 |
SI5345A-D04594-GM 概要
A clock synthesizer / jitter attenuator is a timing integrated circuit that takes a single reference input (crystal, oscillator, or recovered clock) and produces multiple low-jitter output frequencies. These devices sit in the timing-tree hierarchy: clock IC -> clock generator -> frequency synthesizer -> PLL (phase-locked loop). They are commonly used in place of multiple crystal oscillators and PLLs to reduce board area, BOM cost, and EMI leakage.
Key features of this Si5345 variant include 10 independently configurable outputs, per-output frequency synthesis up to 1.028 GHz, programmable output formats (LVDS, LVPECL, HCSL, CMOS, CML), digital jitter attenuation bandwidth programming via ClockBuilder Pro, and independent output enable / frequency scaling registers. The 64-pin QFN exposed-pad package provides a low thermal resistance path to the PCB ground plane.
Internally the Si5345 uses two-stage MultiSynth architecture: a low-jitter integer-N PLL locks to the reference, then each output passes through a fractional-N divider that synthesizes arbitrary rational frequency ratios. Loop bandwidth is digitally programmable (typical 0.1 Hz to 1 kHz) for optimized jitter transfer in PLL cleanup, SONET/SDH, or OTN applications.
Typical applications include wireless base-station timing, OTU/SONET line cards, broadcast SDI/HD-SDI reference clocks, FPGA / ASIC SerDes reference inputs, and high-end professional audio clocks. The 1.7 V to 3.47 V core supply and 1.8 V / 3.3 V IO supplies allow direct interface to most modern FPGAs, SoCs, and ASICs without level translation.
When designing with this part, configure the device once using ClockBuilder Pro, then export the resulting register file and NVM image for production programming. Maintain a clean PCB ground return under the exposed pad and follow the Skyworks Si5345 Reference Manual layout recommendations.
ドロップイン代替品: SI5345A-D04594-GM — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: SI5345A-D04594-GM （同一形状・フットプリント） — 相違点: Package, Control Interface, MSL Level, Output Frequency Range, Supply Voltage.
クイック比較ツール — 並列比較する代替部品を選択:
SI5345A-D-GM
✅ ドロップイン✓ 在庫あり
$27.5 / 個
データシートを見る →SI5345A-D04594-GMR
✅ ドロップイン✓ 在庫あり
$18.1 / 個
データシートを見る →SI5345B-D-GM
✅ ドロップイン✓ 在庫あり
$8.55 / 個
データシートを見る →SI5344A-D-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5342A-D-GM
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SI5345A-D04594-GM 仕様
| 機能 | 10-Channel Any-Frequency, Any-Output Jitter Attenuator / Clock Multiplier |
| 出力数 | 10 |
| Maximum Output Frequency | 1.028 GHz |
| Input Frequency Range | 10 MHz to 750 MHz (typical reference) |
| Output Formats | LVDS / LVPECL / HCSL / CML / CMOS (per-output programmable) |
| RMS Jitter | < 200 fs typical (12 kHz to 20 MHz integration) |
| Jitter Attenuation Bandwidth | Digitally programmable (0.1 Hz to 1 kHz range) |
| Core Supply Voltage | 1.8 V (typical) |
| Operating Supply Range | 1.71 V to 3.47 V |
| Configuration Interface | I2C / SPI (with on-chip NVM) |
| Reference Input | Crystal or single-ended/differential clock |
| パッケージ | 64-VFQFN Exposed Pad (10x10 mm) |
| 実装タイプ | Surface Mount |
| 動作温度 | -40 C to +85 C |
| MSLレベル | 2 |
| RoHS ステータス | Compliant |
SI5345A-D04594-GM 64-vfqfn exposed pad (10x10 mm) ピン配置ガイド
SI5345A-D04594-GM (64-vfqfn exposed pad (10x10 mm) パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: SI5345A-D04594-GM.
詳細は データシート をご参照ください。
主な用途
SI5345A-D04594-GM の用途: 6 件s: 10G/25G/100G Ethernet Switch Reference Clocks, OTU / SONET / SDH Line Card Timing, Broadcast SDI / HD-SDI Reference Clock, FPGA / ASIC SerDes Reference Generation, Wireless Base Station Timing, Professional Audio Clock Distribution.
10G/25G/100G Ethernet Switch Reference Clocks
The SI5345A-D04594-GM serves as the central reference-clock generator for high-density Ethernet switches and routers. With sub-200 fs RMS jitter, it directly meets IEEE 802.3bm and OIF-CEI reference-clock budgets for 10G, 25G, and 100G SerDes. Ten independently configurable outputs let one part fan out to multiple PHY ASICs or switch fabrics without needing separate crystal oscillators per lane. Place the device adjacent to the SerDes reference pins, route differential outputs with 100 ohm impedance, and follow the Si5345 Family Reference Manual layout stackup. The 1.71-3.47 V core supply rails let the part run from the same 1.8 V or 3.3 V rail as the FPGA or SoC, simplifying power sequencing.
おすすめ
OTU / SONET / SDH Line Card Timing
Telecom line cards need extremely low-jitter clocks to drive SONET/SDH, OTU, and OTN framers. The SI5345A-D04594-GM's digitally programmable jitter attenuation bandwidth (0.1 Hz-1 kHz) lets designers tune loop bandwidth to track incoming PTP or SyncE references while rejecting wander and high-frequency phase noise. Per-output LVDS and LVPECL formats align directly with framer and Muxponder ASIC reference inputs. The factory-programmed -D04594- NVM image eliminates in-system programming on production line cards, simplifying manufacturing flow. For OTU4 applications requiring even tighter jitter, migrate to the Si5345B-D-GM (lower-jitter B-grade) variant.
おすすめ
Broadcast SDI / HD-SDI Reference Clock
Studio broadcast and pro-AV routers need a single 148.5 MHz / 148.5/1.001 MHz reference for SDI video paths. The SI5345A-D04594-GM delivers these video rates from a 27 MHz video reference, while additional outputs can drive audio clocks, timecode, and HDMI reference rails. The any-format, any-output MultiSynth architecture removes the need for separate generator PLLs per rate, simplifying PCB. Drive each output with HCSL or LVDS to meet SMPTE 259M/292M/424M and ST 2059-2 jitter masks. Configure once with ClockBuilder Pro, burn to NVM in production, and replace end-of-life discrete PLL trees.
おすすめ
FPGA / ASIC SerDes Reference Generation
High-end FPGAs and ASICs require multiple low-skew reference clocks for embedded SerDes, transceivers, and DSP blocks. The SI5345A-D04594-GM's ten MultiSynth outputs can simultaneously deliver 156.25 MHz, 161.13 MHz, 312.5 MHz, and other gigabit-rate references to a single package. Sub-200 fs RMS jitter lets the device drive 28 Gbps SerDes with margin. Use each output's programmable slew rate and amplitude to match PCB channel losses without external series terminations. The exposed pad provides a low-thermal-resistance path, important for high-output-count configurations that draw higher device current.
おすすめ
Wireless Base Station Timing
4G/LTE and 5G base stations require multiple synchronized RF reference clocks derived from a common GPS-disciplined reference. The SI5345A-D04594-GM's jitter attenuator mode cleans up the incoming SyncE or PTP timing reference, distributing low-noise clocks to the radio card, baseband ASIC, and fronthaul interfaces. The 64-QFN package and exposed thermal pad suit compact RRH (remote radio head) enclosures. Configure the loop bandwidth to the lowest setting to maximize wander rejection for outdoor deployments. Per-output enable lets the system put unused outputs into Hi-Z for power savings.
おすすめ
Professional Audio Clock Distribution
High-end pro-audio digital mixers, sample-rate converters, and audio interface cards require multiple Word Clock and Super Clock outputs from a single reference. The SI5345A-D04594-GM's any-output programming can deliver 44.1 kHz, 48 kHz, and 96 kHz word-clock rates plus AES3 reference clocks simultaneously. Sub-200 fs jitter keeps converters' SNR and THD specifications within spec by eliminating clock-induced jitter. CMOS output formats drive long-distance cable equalizers directly. Use ClockBuilder Pro to define an NVM image tailored to a given studio's clocking plan, then lock frequencies across multiple boards via a single reference input.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SI5345A-D04594-GM — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SI5345A-D-GM | SI5345A-D04594-GMR | SI5345B-D-GM | SI5344A-D-GM | SI5342A-D-GM |
|---|---|---|---|---|---|---|
| Brand | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks | Skyworks |
| Package | 64-VFQFN Exposed Pad | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same | 64-VFQFN Exposed Pad - same |
| Number of Outputs | 10 | 10 | 10 | 10 | 4 | 2 |
| Maximum Output Frequency | 1.028 GHz | 1.028 GHz | 1.028 GHz | 1.028 GHz | 1.028 GHz | 1.028 GHz |
| Jitter Grade | A-grade | A-grade | A-grade | B-grade (lower jitter) | A-grade | A-grade |
| RMS Jitter | <200 fs | <200 fs | <200 fs | <150 fs | <200 fs | <200 fs |
| NVM Configuration | Pre-programmed -D04594- | Default / unprogrammed | Pre-programmed -D04594- | Default / unprogrammed | Default / unprogrammed | Default / unprogrammed |
| Operating Temperature Range | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C | -40C to +85C |
| Configuration Tool | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro | ClockBuilder Pro |
主な差別化要因
- Pre-configured NVM -D04594- image eliminates in-system programming （vs SI5345A-D-GM)
- Lower RMS jitter than A-grade for OTU4 / 100G+ line cards （vs SI5345B-D-GM)
- 10-output density vs 4-output family sibling （vs SI5344A-D-GM)
設計ノート
Recommended: Provide a continuous ground plane under the 64-VFQFN exposed pad with at least 8 thermal vias to the inner-layer ground pour. Stitch the four inner rows of ground pins with 0.5 mm ground traces to the central pad. According to the Si5345 Family Reference Manual, ground-via stitching directly under the exposed pad significantly improves output jitter and reduces spurious noise. For multi-layer boards, place the Si5345 on the top layer and keep high-speed outputs on adjacent reference layers with a 100 ohm differential microstrip.
Decouple each VDD pin with a 0.1 uF X7R ceramic capacitor placed within 1 mm of the pin, plus one 10 uF bulk capacitor per supply rail on the same board side. Use a ferrite bead on the analog VDD supply if it is derived from the digital rail. According to the Skyworks Si5345 datasheet, poor decoupling increases output jitter and may cause PLL lock failure. Power-up sequencing requires the core 1.8 V supply to rise before the IO supplies; use an RC delay or power-good signal from a supervisor IC if your system cannot guarantee this ordering.
Estimated: For 1028 MHz LVDS output into a 50 ohm receiver with 100 ohm differential trace, expected intra-pair skew should stay below 5 ps if trace length matching is held within 0.5 mm and the differential pair is routed over a continuous reference plane. Maintain 3W spacing between adjacent differential pairs to suppress crosstalk. Add a 100 ohm differential termination resistor at the receiver end; do not place a series termination on the driver side for LVDS. For HCSL outputs, use the Si5345's internal source termination to control rise time and meet PCI Express jitter-compliance requirements.
Common pitfalls: (1) Do not share an input reference with multiple Si5345 parts without buffering - each Si5345 expects to drive its own PLL directly. (2) Do not program the NVM image until the ClockBuilder Pro project has been fully validated on the Si5345-D-EVB evaluation board. (3) Watch out for the difference between SI5345A-D-GM (default NVM) and SI5345A-D04594-GM (pre-programmed -D04594- frequency plan) - selecting the wrong variant forces on-board programming. (4) Ensure I2C/SPI bus pull-ups are present even if you program via one-time NVM; they are required for status reads.
コンプライアンス情報
RoHS and REACH compliant per Skyworks product page. Halogen-free per Skyworks Si5345 family datasheet. Not AEC-Q100 qualified (consumer/commercial/industrial timing IC).
