SIC462ED-T1-GE3 - 60V, 6A Sync Buck Regulator | Vishay microBUCK
部品番号: SIC462ED-T1-GE3 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $3.45 | $3.45 |
| 10 | $3.1 | $31.00 |
| 100 | $2.65 | $265.00 |
| 500 | $2.3 | $1,150.00 |
| 1,000 | $2.05 | $2,050.00 |
| 3,000 | $1.8 | $5,400.00 |
SIC462ED-T1-GE3 概要
A synchronous buck regulator (also called a step-down switching converter) is a switch-mode power supply topology that uses a high-side MOSFET, a low-side synchronous rectifier MOSFET, an inductor and output capacitors to convert a higher DC input voltage to a lower DC output voltage with high efficiency. Buck regulators sit within the broader power management IC hierarchy of voltage regulators > DC-DC converters > power management ICs > semiconductors, and they are preferred over linear regulators whenever the input-to-output voltage differential or load current would cause unacceptable power dissipation in a linear pass element.
Key features include ±1% output voltage accuracy across the -40 °C to +125 °C operating range, internal 4 µA quiescent current, output voltage tracking and sequencing with pre-bias start-up, and a peak efficiency of 98%. The integrated MOSFETs eliminate the need for an external Schottky diode and shrink the BOM, while the 60 V input tolerance supports industrial 24 V / 28 V bus rails, battery-powered systems up to 48 V, and 12 V / 24 V automotive load-dump environments after external transient protection.
Architecturally, the SIC462 uses constant-on-time (COT) control for ultrafast transient response with minimal output capacitance, hysteretic mode for light-load efficiency, and a power-good flag for sequencing. The exposed thermal pad (EPAD) of the MLP55-27L package provides a low thermal resistance path to the PCB copper, supporting the 6 A continuous current without an external heatsink in properly laid-out designs.
Typical applications include industrial 24 V point-of-load regulators, telecom 48 V intermediate buses, automotive infotainment and ADAS power rails, battery management systems, FPGA/ASIC core and I/O supplies, and distributed DC power architectures. This page synthesizes distributor pricing, pin-compatible microBUCK alternatives, and practical PCB layout notes not found in the manufacturer datasheet.
ドロップイン代替品: SIC462ED-T1-GE3 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
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SiC461ED-T1-GE3
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SiC463ED-T1-GE3
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SiC464ED-T1-GE3
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SIC462ED-T1-GE3 最大定格＆電気的特性
| Manufacturer | Vishay Siliconix (Vishay Intertechnology) |
| Part Family | microBUCK SiC46x |
| トポロジー | Synchronous Buck (Step-Down) DC/DC Converter |
| 入力電圧範囲 | 4.5 V to 60 V |
| 出力電圧範囲 | Adjustable, 0.8 V to VIN (down to 0.8 V) |
| Output Current (Continuous) | 6 A |
| スイッチング周波数 | Up to 2 MHz |
| Peak Efficiency | 98% |
| Full-Load Efficiency | 95% |
| 静止電流 | 4 µA (typ) |
| Output Voltage Accuracy | ±1% (across -40 °C to +125 °C) |
| Control Architecture | Constant-On-Time (COT) with hysteretic light-load mode |
| 動作温度範囲 | -40 °C to +125 °C |
| パッケージ | PowerPAK MLP55-27L (5 mm x 5 mm), 27 leads + exposed pad |
| 実装タイプ | Surface Mount |
| 特長 | Pre-bias start-up, output voltage tracking/sequencing, power-good flag |
| Integrated MOSFETs | High-side + low-side N-channel MOSFETs (synchronous rectifier) |
| RoHS ステータス | Compliant |
SIC462ED-T1-GE3 ピン構成
| ピン 1 | PGND — Power ground (low-side MOSFET source) |
| ピン 2 | PGND — Power ground (low-side MOSFET source) |
| ピン 3 | PGND — Power ground (low-side MOSFET source) |
| ピン 4 | BOOT — Bootstrap capacitor for high-side gate driver |
| ピン 5 | PHASE — Switch node - return of high-side gate driver, connects to inductor |
| ピン 6 | PHASE — Switch node - return of high-side gate driver |
| ピン 7 | VIN — Power stage input voltage |
| ピン 8 | VIN — Power stage input voltage |
| ピン 9 | VIN — Power stage input voltage |
| ピン 10 | EN — Enable / UVLO threshold adjustment |
| ピン 11 | PGOOD — Power-good output flag |
| ピン 12 | AGND — Analog ground (return for FB and internal references) |
| ピン 13 | FB — Feedback input from external resistor divider |
| ピン 14 | VCC — Internal 5 V LDO output (bypass cap required) |
| ピン 15 | NC — Not connected (per datasheet) |
| ピン 16 | NC — Not connected (per datasheet) |
| ピン 17 | VIN — Power stage input voltage |
| ピン 18 | VIN — Power stage input voltage |
| ピン 19 | PHASE — Switch node - connects to inductor |
| ピン 20 | PHASE — Switch node - connects to inductor |
| ピン 21 | PGND — Power ground |
| ピン 22 | PGND — Power ground |
| ピン 23 | PGND — Power ground |
| ピン 24 | PGND — Power ground |
| ピン 25 | PGND — Power ground |
| ピン 26 | PHASE — Switch node |
| ピン 27 | PHASE — Switch node |
主な用途
SIC462ED-T1-GE3 の用途: 6 件s: Industrial 24 V Point-of-Load (POL) Regulator, Telecom 48 V Intermediate Bus Converter, Automotive 12 V / 24 V Infotainment Power, Battery Management & Energy Storage Systems, FPGA / ASIC Core and I/O Voltage Supplies, Distributed DC Power Architecture (POL).
Industrial 24 V Point-of-Load (POL) Regulator
The SIC462ED-T1-GE3 is purpose-built for industrial 24 V bus rails, accepting 4.5-60 V input per Vishay datasheet 65124 and delivering up to 6 A at 95% full-load efficiency. In a typical PLC or industrial controller, the 24 V backplane feeds the SIC462, which steps down to 5 V, 3.3 V or 1.8 V rails for the MCU, FPGA and sensors. The 60 V input tolerance provides headroom against inductive transients on long 24 V cables, eliminating the need for upstream TVS clamps in most installations. COT control keeps the output stable even with fast load steps from motor drivers or relay coils.
おすすめ
Telecom 48 V Intermediate Bus Converter
In telecom and networking equipment, the SIC462ED-T1-GE3 converts a 48 V (36-60 V) bus to a lower intermediate rail (typically 12 V or 5 V) at 6 A continuous load, as specified in Vishay datasheet 65124. The high input voltage range directly accommodates the standard ETSI/ATIS telecom bus, eliminating a front-end preregulator. Synchronous rectification drives 95-98% efficiency at full load, reducing heatsinking requirements in fan-cooled line cards. The MLP55-27L package's exposed pad allows direct solder attachment to the inner ground plane for low thermal resistance.
おすすめ
Automotive 12 V / 24 V Infotainment Power
The SIC462ED-T1-GE3's 4.5-60 V input range and -40 °C to +125 °C operating range suit 12 V automotive infotainment, ADAS and instrument-cluster power rails, per Vishay datasheet 65124. It supplies the head-unit SoC, audio codec and display backlight from the battery rail, surviving cold-crank and load-dump transients when paired with an upstream TVS. Pre-bias start-up prevents back-feeding the output capacitors during power sequencing with other rails, critical for automotive MCU and DSP power-on requirements. The 6 A output supports multi-rail consolidation behind a single buck IC.
おすすめ
Battery Management & Energy Storage Systems
For battery-powered systems up to 48 V (e-bikes, power tools, telecom battery backup, solar battery management), the SIC462ED-T1-GE3 steps down from the pack voltage to logic rails at up to 6 A, per Vishay datasheet 65124. The 4 µA quiescent current minimizes standby drain on Li-ion packs, extending shelf life and storage endurance. COT control maintains regulation even as the pack voltage sags during discharge, and the high-side MOSFET's 60 V rating tolerates fully-charged 48 V LiFePO4 or 13S Li-ion packs. Efficiency at 95% reduces thermal stress in sealed enclosures.
おすすめ
FPGA / ASIC Core and I/O Voltage Supplies
The SIC462ED-T1-GE3 delivers the high-current low-voltage rails (1.0 V core, 1.8 V auxiliary, 3.3 V I/O) required by modern FPGAs and ASICs from a 12 V or 24 V intermediate bus, per Vishay datasheet 65124. Up to 2 MHz switching frequency allows small inductor and capacitor selection, keeping the power stage footprint under 100 mm². COT control responds in microseconds to load transients from logic activity bursts, maintaining tight Vcore tolerance during dynamic load steps. Power-good flag enables multi-rail sequencing for safe FPGA configuration startup.
おすすめ
Distributed DC Power Architecture (POL)
In distributed power architectures the SIC462ED-T1-GE3 acts as a downstream point-of-load converter from an intermediate 12 V or 24 V bus, providing local 6 A regulation at high efficiency, per Vishay datasheet 65124. Each board function gets its own dedicated POL regulator, reducing distribution losses and improving transient response versus a centralized supply. The MLP55-27L footprint allows dense placement near load ICs, minimizing PCB copper losses and EMI. Scalability within the SiC46x family (2/4/6/10 A pin-compatible) supports varied rail budgets from a single layout.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SIC462ED-T1-GE3 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SiC461ED-T1-GE3 | SiC463ED-T1-GE3 | SiC464ED-T1-GE3 |
|---|---|---|---|---|
| Brand | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology | Vishay Intertechnology |
| Package | PowerPAK MLP55-27L (5x5 mm) | PowerPAK MLP55-27L (5x5 mm) - same | PowerPAK MLP55-27L (5x5 mm) - same | PowerPAK MLP55-27L (5x5 mm) - same |
| Output Current (Continuous) | 6 A | 10 A (+67%) | 4 A (-33%) | 2 A (-67%) |
| Input Voltage Range | 4.5 V to 60 V | 4.5 V to 60 V | 4.5 V to 60 V | 4.5 V to 60 V |
| Output Voltage Range | 0.8 V to VIN (adj) | 0.8 V to VIN (adj) | 0.8 V to VIN (adj) | 0.8 V to VIN (adj) |
| Peak Efficiency | 98% | 98% | 98% | 98% |
| Switching Frequency (max) | 2 MHz | 2 MHz | 2 MHz | 2 MHz |
| Quiescent Current | 4 µA | 4 µA | 4 µA | 4 µA |
| Control Architecture | COT / hysteretic | COT / hysteretic | COT / hysteretic | COT / hysteretic |
主な差別化要因
- Wide 4.5-60 V input range in compact 5x5 mm footprint （vs SiC463ED-T1-GE3 (4 A))
- Highest current in family without sacrificing efficiency （vs SiC461ED-T1-GE3 (10 A))
- Pin-compatible scalability across 2-10 A in one footprint （vs SiC464ED-T1-GE3 (2 A))
設計ノート
Estimated: at VIN=24 V, VOUT=5 V, IOUT=6 A, the SIC462ED-T1-GE3 dissipates roughly (24-5)*6 = 114 mW * 19 V = 2.16 W (input power minus output power; actual switching/conduction losses increase this by ~10-20%). The MLP55-27L package datasheet thermal resistance theta_JA on a 4-layer 1 oz JEDEC test board is around 36 C/W; solder the exposed thermal pad to a continuous ground copper pour of at least 1 square inch to keep the junction rise below 50 C at 2 W dissipation. For sustained 6 A operation at VIN > 30 V, add a topside copper pour stitched to inner ground planes with thermal vias.
Per Vishay datasheet 65124, place the input ceramic bypass capacitors (2x 10 µF X7R minimum, low-ESR) as close as possible to the VIN pins, and connect the PGND pins to a single unified ground plane with wide copper pours to the exposed pad. The PHASE node carries high dV/dt (>60 V in nanoseconds) and must be minimized in loop area to the input capacitors and the bootstrap capacitor to limit ringing and EMI. Use 4-layer PCB with continuous ground plane for best EMI performance; route the FB trace away from PHASE and BOOT to avoid noise injection into the feedback node.
Do not float the EN pin - tie to VIN through a resistor divider if precise UVLO threshold is required, otherwise connect directly to VIN for always-on operation. The BOOT capacitor (typically 0.1 µF X7R) must be placed within 2 mm of the BOOT and PHASE pins; missing this capacitor prevents high-side drive and the regulator will not start. The FB resistor divider must use 1% tolerance resistors referenced to the 0.8 V internal reference; values of 10 kΩ-100 kΩ are recommended to minimize quiescent current draw through the divider. The exposed pad (EPAD) must be soldered to the PCB - dry-jointing the EPAD can cause thermal runaway under load.
コンプライアンス情報
RoHS and lead-free confirmed via Vishay part marking suffix (-GE3 denotes lead-free halogen-free matte tin plating). Not AEC-Q100 qualified - automotive AEC-Q100 grade is not available in the SiC46x family; for AEC-Q100 60 V synchronous buck, use SiC931 or SiC931-Q1 family.
