SN65LVDS93ADGGR - LVDS Serializer 10-135MHz 56-TSSOP | TI
部品番号: SN65LVDS93ADGGR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.2 | $6.20 |
| 10 | $5.58 | $55.80 |
| 100 | $4.65 | $465.00 |
| 500 | $3.95 | $1,975.00 |
| 1,000 | $3.41 | $3,410.00 |
SN65LVDS93ADGGR 概要
An LVDS (Low-Voltage Differential Signaling) serializer is an interface IC that compresses a wide parallel data bus onto a small number of high-speed differential pairs, dramatically reducing connector size, cable count, and EMI between a host processor and a display or backplane. Within the signal-chain hierarchy, it belongs to the SerDes (serializer/deserializer) family of high-speed interface products, sitting between parallel LVTTL logic and LVDS physical-layer line drivers.
Key features of the SN65LVDS93A include 28:4 data channel compression delivering up to 1.904 Gbps serialized throughput per the datasheet, an integrated 7x clock synthesizer that multiplies the input reference clock, and five LVDS line drivers meeting the TIA/EIA-644 LVDS standard for low EMI differential signaling. The A-suffix version extends the supported operating range to 10 MHz - 135 MHz, making it faster than the base SN65LVDS93, which is specified from 20 MHz to 68 MHz on TI.com.
Architecturally, the device contains four 7-bit parallel-load serial-out shift registers, the 7x PLL clock synthesizer, and five LVDS drivers in a single IC. Data is latched on the parallel clock, shifted out at 7x rate, and transmitted with the embedded clock pair so a matching deserializer such as the SN65LVDS96 or DS90CF384 can recover timing without a separate clock channel. LVDS current-mode drivers on a 3.3V supply produce approximately 350 mV differential swings with low skew.
Typical applications include TFT-LCD panel interfacing in industrial displays and medical monitors, video transmission between a graphics controller and a FlatLink-compatible display, and point-to-point board-to-board links where a 28-bit parallel bus must cross a flex cable or backplane with minimal wiring.
When designing with this device, keep the parallel input setup/hold times within datasheet limits and route the LVDS pairs as controlled-impedance 100-ohm differential traces; also confirm the exact input clock range against your system, since TI lists both a 10-135 MHz range (A version) and 20-68 MHz (base part) across product pages.
This page synthesizes distributor inventory data, drop-in alternatives, pinout guidance, and practical design notes not found in the manufacturer datasheet alone, with pricing refreshed as of 2026-10-19.
ドロップイン代替品: SN65LVDS93ADGGR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SN65LVDS93BDGG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN65LVDS93AIDGGRQ1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN65LVDS93ADGG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN75LVDS83ADGG
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN75LVDS83BDGGR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN65LVDS93ADGGR 仕様
| 機能 | LVDS SerDes Transmitter (Serializer), FlatLink |
| Input Channels | 28 (single-ended LVTTL parallel data) |
| Output Channels | 4 LVDS data pairs + 1 LVDS clock pair |
| Serialization Ratio | 28:4 |
| Input Clock Range | 10 MHz to 135 MHz (SN65LVDS93A) |
| Throughput | Up to 1.904 Gbps serialized |
| Clock Synthesizer | 7x clock multiplication PLL |
| 電源電圧 | 3.3 V (typical) |
| Differential Output Swing | Approx. 350 mV (LVDS, TIA/EIA-644) |
| 動作温度 | -40C to +85C |
| パッケージ | 56-TSSOP (DGG), 56-TFSOP, 6.10 mm width |
| 実装タイプ | Surface Mount |
| Protocol / Interface | LVDS (FlatLink transmitter) |
| Data Rate Classification | 10 MHz - 135 MHz LVDS SerDes Transmitter |
| RoHS ステータス | unknown |
SN65LVDS93ADGGR 56-tssop (dgg), 56-tfsop, 6.10 mm width ピン配置ガイド
SN65LVDS93ADGGR (56-tssop (dgg), 56-tfsop, 6.10 mm width パッケージ) のピン配置。 ピン番号、機能、接続図はメーカーのデータシートで定義されています。正確なフットプリントとはんだ付けのガイドラインについては、データシートを参照してください。
詳細なピン配置データはありません: SN65LVDS93ADGGR.
詳細は データシート をご参照ください。
主な用途
SN65LVDS93ADGGR の用途: 6 件s: TFT-LCD Panel Interface, Industrial Display Systems, Medical Monitoring Displays, Point-to-Point Board-to-Board Links, Test and Measurement Instrument Video, Automotive Display Development (Q1 path).
TFT-LCD Panel Interface
The SN65LVDS93ADGGR is purpose-built for driving TFT-LCD panels with integrated LVDS receivers. It accepts a 28-bit parallel RGB pixel bus from a graphics controller and serializes it onto four LVDS data pairs plus a clock pair, reducing a wide ribbon cable to a compact low-EMI differential link. The 10 MHz to 135 MHz input clock range covers panel resolutions from VGA-class through high-resolution displays, while the approx. 350 mV LVDS differential swing keeps radiated emissions low across flex or cable runs between main board and panel. Place the serializer close to the controller's parallel output port and route the five pairs as 100-ohm controlled-impedance differential traces with matched lengths to preserve pixel timing.
おすすめ
Industrial Display Systems
In industrial HMI terminals, machine-vision monitors, and factory automation displays, the SN65LVDS93ADGGR provides a rugged video link with -40C to +85C operation suited to unconditioned environments. Its LVDS current-mode drivers resist common-mode noise from motor drives and switching supplies on the factory floor, and the serialized 5-pair link withstands the flexing and routing constraints of display arms and enclosures better than a 28-conductor parallel cable. With pixel clocks up to 135 MHz, it supports modern widescreen operator panels. Designers should budget setup/hold margins for the parallel bus and add common-mode chokes on the LVDS pairs where cables exit the enclosure for enhanced EMC performance.
おすすめ
Medical Monitoring Displays
Medical patient monitors and diagnostic displays demand both high image quality and low electromagnetic emissions to coexist with sensitive analog front-end circuitry. The SN65LVDS93ADGGR meets these needs with approx. 350 mV low-swing differential signaling that minimizes EMI near ECG/EEG amplifiers, and its 10-135 MHz range supports the high-resolution panels used in ultrasound and surgical visualization. The serialized link reduces the number of conductors crossing isolation and cable-gland boundaries, simplifying cable design. Verify the clock range against the target panel timing, and route the LVDS pairs away from patient-lead inputs; the -40C to +85C range covers typical clinical equipment environments.
おすすめ
Point-to-Point Board-to-Board Links
Beyond displays, the SN65LVDS93ADGGR generalizes to any 28-bit parallel bus that must cross a backplane, mezzanine connector, or cable with reduced pin count. Using the 28:4 FlatLink serialization, a 28-conductor plus ground interface shrinks to five differential pairs plus ground, cutting connector cost and improving signal integrity at speed. Throughput reaches 1.904 Gbps per the datasheet, adequate for many framing and data-transport applications. Pair the transmitter with a FlatLink-compatible deserializer and embed the clock pair for timing recovery without a separate clock channel. Ensure both boards share a common ground reference and keep stubs off the differential pairs to avoid reflections at multi-hundred-MHz toggle rates.
おすすめ
Test and Measurement Instrument Video
Bench instruments and automated test equipment frequently use separate graphics boards and LCD assemblies, requiring a clean high-speed video path between them. The SN65LVDS93ADGGR transmits the 28-bit pixel bus from the instrument's FPGA or graphics controller across the internal harness at pixel clocks up to 135 MHz, its catalog-grade -40C to +85C range being sufficient inside temperature-controlled laboratories. LVDS signaling keeps switching noise out of sensitive measurement front ends, an important consideration in spectrum analyzers and digitizers. Power the serializer from a well-bypassed 3.3V rail; Heisener reports 15,588 pieces in stock, simplifying production sourcing for instrument builders.
おすすめ
Automotive Display Development (Q1 path)
For automotive center-stack and cluster displays, the pin-compatible AEC-Q100 variant SN65LVDS93AIDGGRQ1 allows designers to develop with the standard SN65LVDS93ADGGR and drop in the Q1 part for production. TI's E2E forum notes the Q1 version has somewhat different thermal properties and ESD standard coverage, so validate both datasheets during the transition. The serialized 5-pair FlatLink link reduces harness weight and EMI in the vehicle environment, where wide parallel video buses would otherwise require heavy shielding. Use the same 28-bit RGB interface and 10-135 MHz clock range, and qualify the LVDS cable assembly for automotive temperature and vibration requirements alongside the IC swap.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SN65LVDS93ADGGR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SN65LVDS93BDGG | SN65LVDS93AIDGGRQ1 | SN75LVDS83ADGG | SN75LVDS83BDGGR |
|---|---|---|---|---|---|
| Package | 56-TSSOP (DGG) | 56-TSSOP (DGG) - same | 56-TSSOP (DGG) - same | 56-TSSOP (DGG) - same | 56-TSSOP (DGG) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Product Family | SN65LVDS93A (FlatLink transmitter) | SN65LVDS93B high-speed series | SN65LVDS93A-Q1 automotive | SN75LVDS83A FlatLink | SN75LVDS83B FlatLink |
| Serialization | 28:4 + clock, 7x clock synthesizer | 28:4 + clock, 7x clock synthesizer | 28:4 + clock, 7x clock synthesizer | 28:4 + clock, 7x clock synthesizer | 28:4 + clock, 7x clock synthesizer |
| Qualification Grade | Catalog (non-automotive) | Catalog | AEC-Q100 automotive | Catalog | Catalog |
主な差別化要因
- Extended 10-135 MHz clock range （vs SN65LVDS93 (base, 20-68 MHz))
- Higher speed margin in B version （vs SN65LVDS93ADGGR)
- AEC-Q100 path without redesign （vs SN65LVDS93AIDGGRQ1)
設計ノート
Route all five LVDS output pairs (four data + one clock) as 100-ohm controlled-impedance differential pairs with matched intra-pair lengths. At a 135 MHz input clock the 7x PLL toggles pairs near 945 MHz, so keep traces short, avoid stubs and vias where possible, and maintain a continuous reference plane beneath each pair. For cable or flex runs to the panel, use twisted-pair or differential flex routing and consider a common-mode choke at the connector for EMC. Verify parallel input setup/hold timing against the TI datasheet values, since violations misalign the serialized bits and appear as pixel errors at the deserializer.
Supply the SN65LVDS93ADGGR from a clean 3.3 V rail with at least 0.1 uF ceramic decoupling at each supply pin of the 56-TSSOP package plus one bulk 4.7-10 uF capacitor nearby. LVDS current-mode drivers draw dynamic current at the 7x-rate edges, and supply ripple couples directly into output jitter, which limits the achievable pixel clock. If the rail also feeds other fast logic, consider a ferrite bead or a low-noise LDO (for example a TI TPS7A-family part) for the serializer island. Estimated: even modest supply noise of tens of millivolts can visibly increase deterministic jitter on a sub-ns bit period.
Do not confuse version frequency ranges: TI.com lists the base SN65LVDS93 at 20-68 MHz while the A version covers 10-135 MHz - substituting the wrong suffix silently limits your pixel clock. The DGGR suffix is only the reel-coded packing of the same DGG die, so footprint is unchanged. If migrating to the automotive SN65LVDS93AIDGGRQ1, review thermal and ESD sections, which differ per TI's E2E forum. Finally, the five LVDS pairs must include the clock pair in the link; omitting it leaves the deserializer without timing recovery and the link will not lock.
コンプライアンス情報
No explicit RoHS/REACH statements were present in the retrieved data; the -Q1 variant (SN65LVDS93AIDGGRQ1) is the automotive-qualified option. Verify compliance on TI's official product page.
