SN74LVC04APWR - Hex Inverter, 1.65-3.6V, 14-TSSOP | Texas Instruments
部品番号: SN74LVC04APWR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $0.41 | $0.41 |
| 10 | $0.35 | $3.50 |
| 100 | $0.25 | $25.00 |
| 500 | $0.18 | $90.00 |
| 1,000 | $0.14 | $140.00 |
| 2,500 | $0.11 | $275.00 |
SN74LVC04APWR 概要
A hex inverter is a fundamental building block in digital logic, falling within the broader category of logic gates, specifically the inverter (NOT gate) family. Inverters are used for signal inversion, clock generation, signal conditioning, and as part of oscillator and Schmitt-trigger circuits. The LVC (Low-Voltage CMOS) sub-family is optimized for low-power, low-voltage operation while maintaining high-speed switching and TTL-compatible inputs, bridging 5 V legacy logic with modern 3.3 V or lower-voltage controllers.
Key features include a maximum propagation delay (tpd) of 4.5 ns at 3.3 V VCC, typical output ground bounce (VOLP) below 0.8 V at VCC = 3.3 V, and ±24 mA output drive capability. The device is specified across three operating temperature ranges: -40 °C to +85 °C, -40 °C to +125 °C, and -55 °C to +125 °C. Inputs are 5.5 V tolerant, eliminating the need for external level shifters when translating from 5 V signals. The 14-TSSOP package offers a compact 5.00 mm × 4.40 mm footprint suitable for high-density PCB layouts.
The SN74LVC04A architecture uses TI's Advanced CMOS (C²MOS) process technology, providing balanced propagation delay and low quiescent power consumption (typically 10 µA). The output structure includes balanced push-pull stages capable of sinking and sourcing ±24 mA, making the device suitable for driving multiple loads or moderate capacitive bus lines. Internal ESD protection exceeds 2 kV HBM per JEDEC standards.
Typical applications include 3.3 V to 5 V logic translation in mixed-voltage designs, clock-signal inversion in microcontroller interfaces, general-purpose signal conditioning in industrial control, oscillator/clock-generation circuits using two inverters with an RC network, and bus-driving in point-to-point communication links. The wide input tolerance (up to 5.5 V) makes this part especially useful as a level shifter from legacy 5 V systems.
When designing with the SN74LVC04A, place decoupling capacitors (0.1 µF ceramic) as close as possible to the VCC and GND pins to minimize switching noise. For high-speed or heavily-loaded outputs, add a series termination resistor near the driver pin to control ringing. Unused inputs should be tied to VCC or GND (not left floating) to prevent shoot-through current.
This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: SN74LVC04APWR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
SN74LVC04APWT
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SN74LVC04APWRG4
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
SN74LVC04AQPWRQ1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
74LVC04APW,118
✅ ドロップイン📋 参考代替品（カタログ未掲載）
MC74LVC04ADTR2G
✅ ドロップイン📋 参考代替品（カタログ未掲載）
SN74LVC04APWR 最大定格＆電気的特性
| Logic Type | Hex Inverter (NOT gate) |
| Number of Channels | 6 |
| Number of Gates | 6 |
| Logic Function | Y = Ā |
| Operating Voltage (VCC) | 1.65 V to 3.6 V |
| Input Voltage Tolerance | Up to 5.5 V |
| Maximum Propagation Delay (tpd) | 4.5 ns at 3.3 V VCC |
| Output Drive Capability | ±24 mA |
| Output Ground Bounce (VOLP) | < 0.8 V typical at VCC = 3.3 V |
| Quiescent Current (ICC) | 10 µA typical |
| 動作温度範囲 | -40 °C to +85 °C / -40 °C to +125 °C / -55 °C to +125 °C |
| Input Logic Levels | CMOS/LVTTL compatible |
| ESD Protection (HBM) | 2 kV (JEDEC) |
| パッケージ | 14-pin TSSOP (PW), 5.00 mm × 4.40 mm |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| MSLレベル | 1 (unlimited) |
SN74LVC04APWR ピン構成
| ピン 1 | 1A — Input 1 |
| ピン 2 | 1Y — Output 1 (inverted) |
| ピン 3 | 2A — Input 2 |
| ピン 4 | 2Y — Output 2 (inverted) |
| ピン 5 | 3A — Input 3 |
| ピン 6 | 3Y — Output 3 (inverted) |
| ピン 7 | GND — Ground |
| ピン 8 | 4Y — Output 4 (inverted) |
| ピン 9 | 4A — Input 4 |
| ピン 10 | 5Y — Output 5 (inverted) |
| ピン 11 | 5A — Input 5 |
| ピン 12 | 6Y — Output 6 (inverted) |
| ピン 13 | 6A — Input 6 |
| ピン 14 | VCC — Power supply (1.65 V to 3.6 V) |
主な用途
SN74LVC04APWR の用途: 6 件s: 5V to 3.3V Logic Level Translation, Crystal Oscillator with Inverter Pair, Clock Signal Inversion for Microcontroller, General-Purpose Signal Conditioning, Reset and Power-Good Signal Generation, LED Driving and Visual Indicators.
5V to 3.3V Logic Level Translation
The SN74LVC04APWR is widely used as a single-supply level shifter between legacy 5 V CMOS/TTL logic and modern 3.3 V microcontrollers. With input thresholds accepting up to 5.5 V regardless of the device's VCC (1.65-3.6 V), a 5 V signal on any input produces a clean 3.3 V CMOS output. According to the TI datasheet SCAS281, this allows one inverter per line without external pull-ups or level-shifter ICs, saving board space. The 4.5 ns propagation delay at 3.3 V is fast enough for SPI, UART, and interrupt signals up to several MHz.
おすすめ
Crystal Oscillator with Inverter Pair
Two channels of the SN74LVC04APWR can be configured as a Pierce oscillator using a quartz crystal, two load capacitors, and a feedback resistor. According to typical TI application notes, this configuration provides a low-cost clock source up to tens of MHz. The LVC family's high input impedance (5 V-tolerant) and ±24 mA output drive make the inverter stage suitable for driving downstream buffers. This is commonly used in microcontroller designs where an external clock or a second clock domain is needed.
おすすめ
Clock Signal Inversion for Microcontroller
The SN74LVC04APWR is commonly used to invert a clock signal in MCU designs where a complementary clock is required for sampling, DDR-style memory interfaces, or differential signaling. With 4.5 ns tpd at 3.3 V and matched channel-to-channel skew, it provides clean inversion for clocks up to 100 MHz. The TSSOP-14 footprint is small enough to place near the MCU clock input. Per TI datasheet SCAS281, the device operates from -40 °C to +125 °C, suiting industrial and automotive-grade applications.
おすすめ
General-Purpose Signal Conditioning
In industrial control and instrumentation, the SN74LVC04APWR functions as a logic-level signal conditioner that buffers, inverts, and shapes noisy digital signals from sensors, encoders, or communication transceivers. Its 5 V input tolerance allows it to interface directly with 5 V sensor outputs while producing clean 3.3 V logic levels for an FPGA or MCU. The ±24 mA output drive is sufficient for driving long PCB traces or moderate capacitive loads in factory automation environments.
おすすめ
Reset and Power-Good Signal Generation
The SN74LVC04APWR is used to invert reset signals or to combine power-good lines from multiple supply rails using an external RC network plus an inverter. According to TI's logic family application notes, an RC-delay + inverter topology creates clean, debounced reset pulses suitable for microcontrollers and FPGAs. Operating from 1.65 V to 3.6 V VCC, the same part can serve in 1.8 V, 2.5 V, or 3.3 V systems, simplifying BOM across multiple product variants.
おすすめ
LED Driving and Visual Indicators
Each output of the SN74LVC04APWR can source or sink up to ±24 mA, sufficient to drive standard indicator LEDs (typically 5-20 mA) through a current-limiting resistor. This is useful in panel indicators, status LEDs, and optical-isolator input stages. The TSSOP-14 footprint provides six independent LED drivers in a single small package, replacing six discrete transistors in compact designs. Operating from 3.3 V, the typical LED forward current of 10 mA through a 330 Ω resistor is well within the part's drive rating.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: SN74LVC04APWR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | SN74LVC04APWT | SN74LVC04APWRG4 | SN74LVC04AQPWRQ1 | 74LVC04APW,118 | MC74LVC04ADTR2G |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Nexperia | onsemi |
| Package | 14-TSSOP (PW) | 14-TSSOP (PW) - same | 14-TSSOP (PW) - same | 14-TSSOP (PW) - same | 14-TSSOP (PW) - same | 14-TSSOP (PW) - same |
| Operating Voltage (VCC) | 1.65 V to 3.6 V | 1.65 V to 3.6 V | 1.65 V to 3.6 V | 1.65 V to 3.6 V | 1.65 V to 3.6 V | 1.65 V to 3.6 V |
| Input Voltage Tolerance | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V | 5.5 V |
| Maximum tpd at 3.3 V | 4.5 ns | 4.5 ns | 4.5 ns | 4.5 ns | 4.5 ns (typical) | 5.0 ns (typical) |
| Output Drive (IOH/IOL) | ±24 mA | ±24 mA | ±24 mA | ±24 mA | ±24 mA | ±24 mA |
| Automotive Grade (AEC-Q100) | No (standard grade) | No | No | Yes (AEC-Q100) | No | No |
| RoHS Compliance | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
主な差別化要因
- 5 V input tolerance at low-voltage VCC for true 5 V-to-3.3 V translation （vs Standard CMOS inverters (e.g., CD4049UB))
- ±24 mA balanced drive in tiny TSSOP-14 package （vs SN74LVC1G04 (single inverter in SC70))
- Automotive-grade variant available in identical footprint （vs 74LVC04APW (Nexperia) and MC74LVC04ADTR2G (onsemi))
設計ノート
Place a 0.1 µF ceramic decoupling capacitor as close as possible to the VCC pin (pin 14) and the GND pin (pin 7) of the SN74LVC04APWR. For designs with multiple LVC devices sharing a supply, add a bulk 1-10 µF tantalum or ceramic capacitor near the regulator output. According to TI's logic-family application guidelines, this decoupling network suppresses VCC bounce caused by simultaneous switching of multiple output channels and prevents logic errors on adjacent gates.
Route high-speed output traces (especially clock-inversion applications) with controlled impedance and avoid parallel runs longer than 25 mm with adjacent signal traces to minimize crosstalk. The TSSOP-14 package's lead pitch is 0.65 mm, so escape routing on inner PCB layers may require micro vias. Keep input traces short to reduce pickup of nearby noise; the 5 V-tolerant input structure can otherwise inject small disturbance into the input pin during fast VCC transitions.
Never leave unused inputs floating on the SN74LVC04APWR. Per the TI datasheet, floating CMOS inputs can drift to mid-supply and cause shoot-through current in the input stage, increasing quiescent current and potentially generating oscillations. Tie unused inputs directly to VCC or GND (the LVC family has no internal pull-ups or pull-downs on inputs). Also ensure input signal rise/fall times are not slower than the tpd rating, or add a Schmitt trigger (e.g., SN74LVC14) for slow edges.
When driving capacitive loads greater than 50 pF (long cables, multiple gate fan-outs), the SN74LVC04APWR output stage may exhibit ringing or non-monotonic edges. According to TI logic-device application notes, adding a 22-33 Ω series resistor at the output pin damps the LC resonance formed by the trace inductance and load capacitance. This preserves signal integrity up to 100 MHz clock frequencies without exceeding the device's 24 mA drive rating.
コンプライアンス情報
RoHS and REACH compliant per TI product page. Standard grade; choose SN74LVC04AQPWRQ1 for AEC-Q100 automotive applications. Lead-free and halogen-free per TI packaging materials declaration.
