THS10082CDAG4 - 10-Bit 8 MSPS Dual-Channel ADC, 32-TSSOP | TI
部品番号: THS10082CDAG4 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.05 | $130.50 |
| 100 | $11.4 | $1,140.00 |
| 500 | $9.95 | $4,975.00 |
| 1,000 | $8.85 | $8,850.00 |
THS10082CDAG4 概要
An ADC (analog-to-digital converter) is a data-conversion integrated circuit that translates continuous-time analog voltage signals into discrete digital codes at a specified sample rate. The THS10082 belongs to the pipelined ADC sub-family of successive-approximation/pipeline hybrid converters used for medium-speed, multi-channel acquisition; it sits within the broader data-converter IC hierarchy under signal-chain and data-acquisition semiconductors. Its dual-channel, simultaneous-sampling architecture makes it specifically suited for capturing paired signals (such as I/Q or voltage/current) without inter-channel timing skew.
The THS10082CDAG4's differentiating features include 2-channel simultaneous sampling at up to 8 MSPS per channel, an integrated 16-word FIFO that decouples the converter's data-rate from the host processor, channel autoscan for sequential conversions, a low-power CMOS pipeline core, and a parallel DSP/uP interface that allows direct connection to C5000/C6000 DSPs and standard microcontrollers. Each channel carries its own sample-and-hold, eliminating inter-channel aperture skew at full speed.
The device uses a multistage pipelined architecture with output error correction, providing 10-bit linearity at 8 MSPS while consuming low total power. The single 3.3 V supply and CMOS I/O simplify power-tree design, while the integrated FIFO allows burst capture of up to 16 conversion results before the host is interrupted, reducing glue logic and easing timing closure in DSP-coupled designs.
Typical applications include radar intermediate-frequency (IF) acquisition, digital imaging front ends, communications baseband I/Q sampling, high-speed data acquisition, and multi-channel industrial instrumentation. The combination of dual channels and a FIFO is particularly useful in motor-control current/voltage sensing, where simultaneous sampling prevents calculation artifacts from phase delay between channels.
A key design consideration is FIFO depth: with only 16 words of buffer, the host must service interrupts often enough to avoid overrun, so DMA or DSP-interrupt-driven reads are recommended. Input bandwidth and the external drive amplifier must also support the 8 MSPS Nyquist envelope; an antialiasing filter ahead of AINP/AINN is required to prevent out-of-band foldback.
This page synthesizes distributor pricing from Octopart and DigiKey, drop-in TSSOP-32 footprint alternatives (including automotive-grade and full-speed same-die variants), and practical design notes on FIFO management and input driving that are not collected in a single location in the manufacturer datasheet.
ドロップイン代替品: THS10082CDAG4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
THS10082IDAG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS10082CDA
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS10082IDA
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS10082IDAG4Q1
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS7861IDBQR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS10082CDAG4 最大定格＆電気的特性
| 分解能 | 10 bit |
| Sample Rate | 8 MSPS per channel |
| Number of Input Channels | 2 (simultaneous sampling) |
| Architecture | Multistage pipelined, CMOS |
| 電源電圧 | 3.3 V single supply |
| インターフェース | Parallel DSP/uP, 8/16-bit selectable |
| FIFO Depth | 16 words |
| Channel Autoscan | Yes (hardware-supported) |
| Input Type | Single-ended, differential pair per channel |
| パッケージ | 32-pin TSSOP (DAG) |
| 動作温度範囲 | 0C to +70C |
| Temperature Grade | Commercial |
| Terminal Form | Gull-wing |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
THS10082CDAG4 32-pin tssop (dag) ピン配置ガイド
THS10082CDAG4 (32-pin tssop (dag) パッケージ) のピン配置。 このアナログコンポーネントは、入力、出力、および電源ピンを備えています。オフセットナル、補償、イネーブルピンの設定については、メーカーのデータシートを参照してください。信号調整やアンプ回路に最適です。
詳細なピン配置データはありません: THS10082CDAG4.
詳細は データシート をご参照ください。
主な用途
THS10082CDAG4 の用途: 6 件s: Radar IF Acquisition, Digital Imaging Front End, Communications Baseband Sampling, Multi-Channel Industrial Instrumentation, Motor Control Current/Voltage Sensing, Medical Ultrasound / Diagnostic Imaging.
Radar IF Acquisition
The THS10082CDAG4's 8 MSPS per-channel throughput and simultaneous dual-channel sampling make it well suited to digitizing the in-phase and quadrature (I/Q) baseband signals at the output of a radar IF stage. By capturing both I and Q channels at exactly the same instant via the per-channel sample-and-hold, the device eliminates aperture-skew artifacts that would otherwise create an unwanted image in the FFT output, improving target separation in the range-Doppler map. The integrated 16-word FIFO buffers the 8 MSPS stream while a TI C6000 DSP services bursts via DMA, leaving headroom for chirp processing. Compared to alternate dual ADCs without a FIFO, this part reduces glue logic and simplifies timing closure on parallel-DSP designs.
おすすめ
Digital Imaging Front End
In a digital imaging pipeline, the THS10082CDAG4 can digitize two analog sensor channels simultaneously at 8 MSPS, supporting CCD/CIS analog preprocessing with matched timing. The 10-bit resolution captures the dynamic range needed for pixel luminance while the parallel DSP interface feeds data directly into an image-signal-processing pipeline without handshake delays. Channel autoscan hardware-managed conversion sequencing reduces firmware complexity, and the 32-pin TSSOP footprint allows compact board placement next to the sensor. Designers typically pair the part with a low-noise input driver and a single-pole RC antialiasing filter at ~3.5 MHz to protect Nyquist.
おすすめ
Communications Baseband Sampling
For software-defined-radio (SDR) baseband designs, the THS10082CDAG4 captures two baseband channels (typically I and Q) at 8 MSPS with 10-bit resolution, preserving amplitude balance and DC offset behavior for demodulation. The single 3.3 V supply simplifies the radio power tree, while the small 32-pin TSSOP footprint suits portable and handheld SDR hardware. The integrated 16-word FIFO eases host timing closure so a low-cost microcontroller or DSP can still maintain a non-overrun data stream. When paired with digital decimation in firmware, 10 bits at 8 MSPS yields effective bits comparable to many narrow-band applications.
おすすめ
Multi-Channel Industrial Instrumentation
In factory-automation data-acquisition cards, the THS10082CDAG4's two simultaneously sampled channels remove the timing skew that would otherwise exist when measuring paired signals such as voltage and current on a power line. With industrial-grade variants available in the same family (THS10082IDAG4), the platform extends across commercial and industrial temperature grades without PCB rework. The 16-word FIFO provides burst tolerance against host delays, ideal for PLC and SCADA subsystems that occasionally stall on higher-priority interrupts. Cost per channel is minimized by dual-channel integration vs two discrete single-channel ADCs.
おすすめ
Motor Control Current/Voltage Sensing
Simultaneous current and voltage sensing in a Field-Oriented Control (FOC) motor drive requires both signals captured at the same instant to avoid calculation errors in the Clarke/Park transform. The THS10082CDAG4 satisfies this with two simultaneous sample-and-hold channels at 8 MSPS, more than sufficient for inverter PWM frequencies in the 20-100 kHz range. The integrated FIFO buffers each PWM-edge snapshot so the motor-control DSP can complete the FOC math before the next sample arrives. Designers can place the part on the same board as the TI C2000 InstaSPIN family for a streamlined digital control loop.
おすすめ
Medical Ultrasound / Diagnostic Imaging
In low-cost portable ultrasound or diagnostic imaging front-ends, the THS10082CDAG4 captures two phased-array receive channels with no inter-channel skew, preserving beamforming vector accuracy. The 8 MSPS rate supports many low-MHz ultrasound probes used in vascular and obstetric scanning, while the parallel host interface streams raw data into a DSP or FPGA for time-gain compensation and envelope detection. The 32-pin TSSOP allows compact dense PCB layouts typical of probe handle electronics. Biomedical designs typically migrate to the higher-temp grade TI variant for chassis-mounted electronics; verify IEC 60601 isolation requirements at the system level.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: THS10082CDAG4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | THS10082IDAG4 | THS10082CDA | THS10082IDA | THS10082IDAG4Q1 | ADS7861IDBQR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 32-TSSOP (DAG) | 32-TSSOP (DAG) - same | 32-TSSOP (DAG) - same | 32-TSSOP (DAG) - same | 32-TSSOP (DAG) - same | QSOP-28 (DBQ) |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit | 12 bit |
| Sample Rate | 8 MSPS | 8 MSPS | 8 MSPS | 8 MSPS | 8 MSPS | 0.5 MSPS |
| Input Channels | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous) | 2 (simultaneous SAR) |
| Temperature Grade | Commercial 0C to 70C | Industrial -40C to +85C | Commercial 0C to 70C | Industrial -40C to +85C | AEC-Q100 automotive | Industrial -40C to +85C |
| FIFO Depth | 16 words | 16 words | 16 words | 16 words | 16 words | 2x FIFO (per channel) |
| Supply Voltage | 3.3 V single | 3.3 V single | 3.3 V single | 3.3 V single | 3.3 V single | 5 V single |
主な差別化要因
- Two simultaneously sampled channels with on-chip FIFO （vs ADS7861IDBQR)
- Industrial and automotive siblings in the same footprint （vs THS10082IDAG4 / THS10082IDAG4Q1)
- Parallel DSP/uP interface with FIFO （vs THS10082CDA (no G4 finish code))
設計ノート
FIFO overflow: with only 16 words of buffer the host must service conversions at >= the conversion rate averaged over the FIFO depth. Estimated: at 8 MSPS the 16-word FIFO fills in 2.0 us; any host interrupt latency longer than that with the FIFO enabled will cause data loss. Use DMA or DSP FIFO-aware interrupts and monitor the FIFO-full flag in the status register.
Power-supply decoupling: place a 0.1 uF X7R ceramic bypass directly at each AVDD and DVDD pin, plus a 10 uF tantalum or polymer bulk capacitor at the regulator output. Estimated bypass-loop inductance target is <5 nH - keep vias short and use wide traces or power-plane pours. Split analog and digital grounds and join them under the ADC to avoid digital return currents polluting the analog reference.
Input trace matching: route AIN1P/AIN1N (and AIN2P/AIN2N) as a length-matched differential pair with a characteristic impedance appropriate for the antialiasing filter; mismatch in pair length directly degrades common-mode rejection at higher input frequencies. Keep digital parallel-bus traces (D0-D9, CS, RD, WR, EOC/INT) away from the analog input and reference pins to minimize digital noise coupling into the analog front-end.
Antialiasing filter selection: the THS10082's 8 MSPS per-channel rate sets a Nyquist of 4 MHz. Use a low-pass or band-pass filter ahead of the analog inputs with a cutoff at or slightly below the highest input frequency of interest and at least 40 dB rejection at the Nyquist frequency to prevent out-of-band foldback. The filter must drive the ADC's switched-capacitor input without excessive distortion - use a wide-bandwidth op-amp such as OPA2354 or OPA228 as a buffer.
Reference decoupling: REF and REFB require low-inductance decoupling close to the package pins to keep reference noise low. Estimated: a 0.1 uF X7R plus 10 uF bulk on REFT and REFB is a starting point; refer to the datasheet reference-pin schematic. Reference noise is a primary contributor to ADC SNR/ENOB; never share the reference pin with other dynamic loads.
コンプライアンス情報
G4 suffix in THS10082CDAG4 indicates Pb-free, RoHS-compliant terminal finish per TI ordering nomenclature. AEC-Q100 is not applicable for the CDA commercial variant - choose THS10082IDAG4Q1 for automotive. Halogen-free status not explicitly stated in the verified web data and is marked unknown.
