THS1041IDWR - 10-Bit 40MSPS Low-Power ADC w/ PGA | Texas Instruments
部品番号: THS1041IDWR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $6.74 | $6.74 |
| 10 | $6.07 | $60.70 |
| 100 | $5.39 | $539.00 |
| 500 | $4.85 | $2,425.00 |
| 1,000 | $4.31 | $4,310.00 |
THS1041IDWR 概要
An ADC is a mixed-signal data converter that samples continuous analog waveforms and produces discrete digital codes at a rate determined by its sample clock. The 10-bit 40 MSPS class sits at the intersection of low-power and moderate-speed conversion, well-suited for battery-powered instrumentation and portable imaging. In the broader taxonomy, the THS1041 belongs to successive-approximation / pipelined CMOS ADCs, a sub-family of data converter ICs under the mixed-signal power management and signal chain hierarchy.
Key differentiating features include an integrated differential PGA with programmable gain, an internal precision analog clamp for DC-restored video inputs, and a programmable digital clamp for AC-coupled systems. The device provides standard 10-bit parallel CMOS output and supports both single-ended and differential inputs with internal reference. The low power dissipation enables fan-less operation in space-constrained designs.
The THS1041 uses a pipelined multi-stage architecture with on-chip sample-and-hold and internal bandgap reference, achieving 40 MSPS throughput at sub-100 mW power. The integrated PGA removes the need for external gain stages in many video and IF-sampling designs, simplifying BOM and reducing board area.
Typical applications include digital video broadcast equipment, set-top box digitizers, CCD imaging arrays, portable oscilloscopes, communications IF sampling, and industrial process control. The integrated clamp functions make it especially attractive for video-class signals where DC restoration is required.
When designing with this device, allocate at least one PCB ground plane under the analog and digital sections joined at a single point. The internal clamp is a precision feature that must be configured via the appropriate digital pin strapping at power-up.
This page synthesizes distributor pricing, drop-in alternatives drawn from the same TI THS1041 family and adjacent TI ADC family, and practical design notes not consolidated on any single manufacturer or distributor page.
ドロップイン代替品: THS1041IDWR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: THS1041IDWR （同一形状・フットプリント） — 相違点: RoHS Status, Input Type, Package, Architecture, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
THS1041CPWR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1041CPW
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1041CPWRG4
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1040CPWRG4
✅ ドロップイン✓ 在庫あり
$4.1 / 個
データシートを見る →THS1031IPWRG4
✅ ドロップイン✓ 在庫あり
$3.42 / 個
データシートを見る →THS1031IPWG4
✅ ドロップイン✓ 在庫あり
$3.38 / 個
データシートを見る →THS1041IDWR 最大定格＆電気的特性
| 分解能 | 10 bit |
| Sample Rate | 40 MSPS |
| 電源電圧 | 3 V nominal |
| Power Dissipation | 55.5 mW at 40 MSPS |
| Architecture | CMOS, pipelined |
| Input Configuration | Single-ended / Differential |
| Integrated PGA | Yes, programmable gain |
| Integrated Clamp | Analog clamp and programmable digital clamp |
| Input Type | Analog, DC or AC coupled |
| Reference | Internal |
| Output Interface | Parallel CMOS, 10-bit |
| 動作温度範囲 | -40 C to +85 C (Industrial) |
| パッケージ | 28-SOIC (DW) - 0.295 inch, 7.50 mm width |
| 実装タイプ | Surface Mount |
| MSLレベル | 1 (unlimited) |
| RoHS ステータス | Compliant |
THS1041IDWR ピン構成
| ピン 1 | REFP — Internal reference bypass |
| ピン 2 | REFM — Internal reference ground |
| ピン 3 | AGND — Analog ground |
| ピン 4 | AVDD — Analog supply, 3 V nominal |
| ピン 5 | INP — Positive analog input |
| ピン 6 | INM — Negative analog input |
| ピン 7 | CLAMPIN — Analog clamp input |
| ピン 8 | CLAMPOUT — Analog clamp output |
| ピン 9 | DCBIAS — DC bias for clamp |
| ピン 10 | GAIN0 — PGA gain select bit 0 |
| ピン 11 | GAIN1 — PGA gain select bit 1 |
| ピン 12 | MODE0 — Input mode select bit 0 |
| ピン 13 | MODE1 — Input mode select bit 1 |
| ピン 14 | DGND — Digital ground |
| ピン 15 | DVDD — Digital supply, 3 V nominal |
| ピン 16 | D0 — Data output bit 0 (LSB) |
| ピン 17 | D1 — Data output bit 1 |
| ピン 18 | D2 — Data output bit 2 |
| ピン 19 | D3 — Data output bit 3 |
| ピン 20 | D4 — Data output bit 4 |
| ピン 21 | D5 — Data output bit 5 |
| ピン 22 | D6 — Data output bit 6 |
| ピン 23 | D7 — Data output bit 7 |
| ピン 24 | D8 — Data output bit 8 |
| ピン 25 | D9 — Data output bit 9 (MSB) |
| ピン 26 | DRDY — Data ready strobe |
| ピン 27 | CLK — Sample clock input |
| ピン 28 | PD — Power-down, active high |
主な用途
THS1041IDWR の用途: 6 件s: Digital Video Broadcast Equipment, Set-Top Box Video Digitizer, CCD Imaging Array Digitizer, Portable Digital Oscilloscope, Communications IF Sampling, Industrial Process Control Digitizer.
Digital Video Broadcast Equipment
The THS1041IDWR is well-matched to digital video broadcast receivers and set-top box front-ends because its integrated analog clamp restores DC baseline for composite or component video, eliminating external sync-tip clamping circuitry. At 40 MSPS the converter captures standard-definition video with 4x oversampling for clean decimation to 10-bit pixel data. The internal PGA adds 6-10 dB of gain on weak antenna feeds without an external amplifier stage. Drawing 55.5 mW from a 3 V rail, it suits multi-channel receiver designs where four ADCs operate in parallel without exceeding thermal budgets.
おすすめ
Set-Top Box Video Digitizer
In set-top box architectures, the THS1041IDWR digitizes composite, S-Video, or component inputs with sufficient bandwidth for 13.5 MHz video sampling at 4x oversampling. The integrated programmable digital clamp auto-centers AC-coupled video to mid-scale, removing the sync separator and DC restore logic that historically consumed board area. The parallel CMOS output bus connects directly to MPEG decoders without glue logic. Operating at 3 V from the main SoC rail, the ADC simplifies power design and avoids secondary regulator stages.
おすすめ
CCD Imaging Array Digitizer
The THS1041IDWR suits CCD line-scan and area-array digitizers where its integrated PGA per channel adjusts gain to match CCD output swing and the analog clamp restores DC reference between pixel samples. At 40 MSPS, the converter handles standard VGA-class imaging at up to 40 megapixels per second, suitable for industrial inspection cameras and document scanners. The CMOS parallel output interfaces to FPGAs or image processors directly. Low 55.5 mW dissipation across the operating temperature range of -40 C to +85 C keeps multi-channel arrays within thermal envelope without forced cooling.
おすすめ
Portable Digital Oscilloscope
Handheld and USB oscilloscopes benefit from the THS1041IDWR's 40 MSPS throughput combined with 55.5 mW dissipation, allowing battery-powered designs with 4-8 hour runtime per charge. The internal PGA scales input signals into the ADC's 1 Vpp full-scale range, removing external attenuator stages for low-voltage measurements. The parallel output bus simplifies FPGA-based capture memory interfacing. The 28-SOIC package is hand-solderable for prototype builds and rework-friendly for field-service technicians.
おすすめ
Communications IF Sampling
In IF-stage digitizers for software-defined radio and intermediate-frequency receivers, the THS1041IDWR samples IF frequencies in the 10-20 MHz band at 40 MSPS, allowing digital demodulation downstream. The integrated differential PGA rejects common-mode noise from upstream mixers while amplifying the differential IF signal into the ADC's input range. The differential input mode is configured via pin strapping, matching typical SAW-filter and IF-transformer drive architectures. The 3 V single-supply operation aligns with portable SDR and cognitive-radio platforms.
おすすめ
Industrial Process Control Digitizer
The THS1041IDWR's industrial -40 C to +85 C operating range makes it suitable for factory-floor data acquisition modules monitoring 4-20 mA loop-derived signals and sensor outputs. Its 10-bit resolution covers most process control accuracy requirements, and 40 MSPS throughput supports multiplexed multi-channel scanning. The integrated analog clamp protects the input from over-voltage transients on long sensor cable runs. The 28-SOIC package withstands industrial shock and vibration environments, and the CMOS pipelined architecture provides deterministic latency for closed-loop control loops.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: THS1041IDWR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | THS1041CPWR | THS1041CPW | THS1040CPWRG4 | THS1031IPWRG4 |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-SOIC (DW) | 28-TSSOP (PW) - same pin-out family | 28-TSSOP (PW) - same pin-out family | 28-TSSOP (PW) - same pin-out family | 28-TSSOP (PW) - same pin-out family |
| Resolution | 10 bit | 10 bit | 10 bit | 10 bit | 10 bit |
| Integrated PGA | Yes | Yes | Yes | Yes (same family) | Yes (same family) |
| Operating Temperature Range | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C | -40 C to +85 C (industrial) |
主な差別化要因
- Integrated analog and programmable digital clamp in one chip （vs THS1041CPWR)
- 28-SOIC package for hand-prototyping and field service （vs THS1041CPWR (TSSOP))
- Differential PGA built into the front end （vs Discrete PGA plus ADC)
設計ノート
Estimated: separate analog and digital ground planes joined at a single point near the ADC's AGND/DGND pins is recommended. Place the analog supply decoupling capacitor (typically 0.1 uF ceramic in parallel with 10 uF tantalum) within 5 mm of the AVDD pin. The digital supply should be similarly decoupled to DVDD. Long analog input traces should be guarded by ground pours to minimize digital switching noise coupling into the front-end.
Route the analog input traces as a matched differential pair with 50-ohm characteristic impedance, keeping them short and isolated from digital output bus traces by ground copper. The 28-SOIC package exposes pin 1 (REFP) and pin 2 (REFM) which require local bypass capacitors to AGND; the reference decoupling network is critical to achieve specified SNR performance at full 40 MSPS throughput.
Ensure the input signal common-mode voltage stays within the device's input compliance range when using the internal clamp; out-of-range common mode can saturate the clamp amplifier and corrupt the conversion. Drive the CLK pin with a clean, low-jitter source because aperture jitter directly degrades SNR at high input frequencies. Avoid toggling the PD pin faster than 1 us after power-up to allow the internal reference to settle.
コンプライアンス情報
RoHS compliant per distributor and TI product page data. Not AEC-Q100 qualified. Halogen-free status not stated in provided web data.
