THS1206QDAR - 12-Bit 6 MSPS Quad-Input ADC, 32-TSSOP | Texas Instruments
部品番号: THS1206QDAR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $11.2 | $112.00 |
| 100 | $9.85 | $985.00 |
| 500 | $8.75 | $4,375.00 |
| 1,000 | $7.95 | $7,950.00 |
THS1206QDAR 概要
An analog-to-digital converter is a mixed-signal integrated circuit that quantizes a continuous-time continuous-amplitude analog voltage into a discrete digital code; pipeline ADCs in particular use multiple cascaded stages to achieve high sample rates while preserving resolution. Within the broader taxonomy, the THS1206 belongs to the data-converter IC family, more specifically the successive-approximation / pipelined hybrid SAR-pipeline subfamily, and is classified as a high-speed multi-channel simultaneous-sampling ADC.
The device supports single-ended input ranges of 1.5 Vp-p to 3 Vp-p programmable through internal registers, and accepts either an internal 1.5V reference or an external reference applied at REFP/REFM. Each analog input channel is sampled simultaneously by its own track-and-hold, eliminating inter-channel skew in multi-axis measurement systems. The integrated 16x FIFO decouples ADC throughput from processor response time, allowing the host to retrieve conversions in bursts and reducing interrupt overhead in real-time DSP systems.
Typical applications include multi-axis motion control (motor current feedback), CCD linear-array imaging, communications IF baseband digitizing, and industrial inspection where several sensors must be sampled at the same instant. The wide input bandwidth and simultaneous sampling make the THS1206 particularly suitable for closed-loop servo loops, vibration analysis, and three-phase power monitoring where phase alignment between channels is critical.
When designing with this part, verify that the AVDD/DVDD decoupling follows the datasheet reference layout and that the FIFO threshold is configured to match the host DMA burst length; under-thresholded reads can cause FIFO overflow and lost samples. The Q-grade suffix confirms operation from -40 C to +125 C, suitable for industrial and automotive under-hood deployments.
This page synthesizes distributor pricing, pin-for-pin compatible alternatives within the THS1206 family, and practical design notes not found in the manufacturer datasheet alone.
ドロップイン代替品: THS1206QDAR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
クイック比較ツール — 並列比較する代替部品を選択:
THS1206CDAR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1206IDA
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1206QDA
✅ ドロップイン📋 参考代替品（カタログ未掲載）
THS1206QDAR 最大定格＆電気的特性
| 分解能 | 12 bits |
| Sample Rate | 6 MSPS |
| Number of Analog Inputs | 2 or 4 (configurable, simultaneous sampling) |
| Architecture | Pipelined CMOS ADC |
| 電源電圧 | 4.75 V to 5.25 V (single 5V supply) |
| 入力電圧範囲 | 1.5 Vp-p to 3 Vp-p (programmable, single-ended) |
| 基準電圧 | Internal 1.5 V or external (REFP/REFM) |
| Integral FIFO Depth | 16 words |
| Digital Interface | Parallel, DSP / microprocessor compatible |
| Auto-Scan Channel Sequencer | Yes, programmable |
| 動作温度 | -40 C to +125 C (Q-grade) |
| パッケージ | 32-pin TSSOP (DA) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| Lead-Free | Yes |
THS1206QDAR ピン構成
| ピン 1 | REFP — Positive reference voltage input / internal reference bypass |
| ピン 2 | REFM — Negative reference voltage input / reference ground |
| ピン 3 | AINP1 — Analog input 1 positive |
| ピン 4 | AINM1 — Analog input 1 negative |
| ピン 5 | AVDD — Analog supply voltage (5 V) |
| ピン 6 | AGND — Analog ground |
| ピン 7 | AINP2 — Analog input 2 positive |
| ピン 8 | AINM2 — Analog input 2 negative |
| ピン 9 | AVDD — Analog supply voltage (5 V) |
| ピン 10 | AGND — Analog ground |
| ピン 11 | AINP3 — Analog input 3 positive |
| ピン 12 | AINM3 — Analog input 3 negative |
| ピン 13 | AVDD — Analog supply voltage (5 V) |
| ピン 14 | AGND — Analog ground |
| ピン 15 | AINP4 — Analog input 4 positive |
| ピン 16 | AINM4 — Analog input 4 negative |
| ピン 17 | AVDD — Analog supply voltage (5 V) |
| ピン 18 | AGND — Analog ground |
| ピン 19 | DVDD — Digital supply voltage (5 V) |
| ピン 20 | DGND — Digital ground |
| ピン 21 | D0 — Digital data output bit 0 (LSB) |
| ピン 22 | D1 — Digital data output bit 1 |
| ピン 23 | D2 — Digital data output bit 2 |
| ピン 24 | D3 — Digital data output bit 3 |
| ピン 25 | D4 — Digital data output bit 4 |
| ピン 26 | D5 — Digital data output bit 5 |
| ピン 27 | D6 — Digital data output bit 6 |
| ピン 28 | D7 — Digital data output bit 7 |
| ピン 29 | D8 — Digital data output bit 8 |
| ピン 30 | D9 — Digital data output bit 9 |
| ピン 31 | D10 — Digital data output bit 10 |
| ピン 32 | D11 — Digital data output bit 11 (MSB) |
主な用途
THS1206QDAR の用途: 6 件s: Multi-Axis Motion Control and Servo Loops, CCD Linear-Array Imaging Systems, Communications IF / Baseband Digitizing, Three-Phase Power Monitoring, Industrial Vibration and Acoustic Analysis, Medical Multi-Channel Patient Monitoring.
Multi-Axis Motion Control and Servo Loops
The THS1206QDAR's simultaneous-sampling architecture and 6 MSPS throughput make it well suited to multi-axis servo drive current feedback. Each of the four analog inputs is sampled on the same clock edge, so phase currents from a three-phase motor (with one channel reused for DC-bus voltage) are captured without inter-channel aperture skew. The 12-bit resolution gives 4096 quantization steps, sufficient for current-loop control bandwidths up to a few kHz when paired with a 1 to 5 kHz PWM. The integrated 16-word FIFO lets the DSP service the ADC in burst reads rather than per-sample interrupts, reducing host overhead. Place the THS1206QDAR after the gate-driver stage with 1 nF X7R ceramics on each AVDD pin and a solid ground plane under the analog section for best noise performance.
おすすめ
CCD Linear-Array Imaging Systems
Linear CCD cameras produce a high-speed pixel stream that the THS1206QDAR can digitize at up to 6 MSPS per channel. Two CCD channels can be digitized simultaneously (one for red, one for blue/green split paths), preserving pixel-to-pixel alignment. The integrated auto-scan channel sequencer cycles through the configured inputs without host intervention, freeing the processor to perform color-space conversion or defect detection. Use the internal 1.5 V reference for production simplicity or apply an external low-noise reference at REFP/REFM when calibration stability is critical. The 32-TSSOP footprint keeps the analog chain compact next to the CCD output amplifier.
おすすめ
Communications IF / Baseband Digitizing
Software-defined radio and IF-sampling receivers can feed the THS1206QDAR directly at baseband or low-IF. At 6 MSPS the ADC comfortably covers a 2.5 MHz Nyquist band or a 5 MHz low-IF signal, and the four-input simultaneity allows parallel I/Q channels for two independent receivers. The integrated FIFO decouples the digitizer from the host DSP, so the FPGA or DSP can read conversions in 8-word bursts and still keep up at full 6 MSPS rate. Use a clean 5 V analog supply with a ferrite bead separating AVDD and DVDD rails to keep switching noise out of the converter front end.
おすすめ
Three-Phase Power Monitoring
Three-phase energy meters require simultaneous voltage and current measurements to compute real power accurately. The THS1206QDAR digitizes up to four signals - three phase voltages (after resistive dividers) plus one phase current (after a shunt) - at the same instant, eliminating the phase error that plagues time-multiplexed ADCs. At 6 MSPS the device captures far more bandwidth than 50/60 Hz mains require, leaving headroom for harmonic analysis up to the 31st or 63rd. The FIFO plus auto-scan simplify the metrology software, and the Q-grade -40 C to +125 C rating supports outdoor cabinet base and secondary voltages.
おすすめ
Industrial Vibration and Acoustic Analysis
Vibration monitoring of rotating machinery demands tight phase alignment between accelerometer channels. The THS1206QDAR samples four IEPE/charge-mode accelerometers simultaneously, allowing FFT-based modal analysis with no inter-channel phase error. Bandwidth of 3 MHz easily captures vibration signatures well past the typical 10 kHz machine-bearing frequency range. The 32-TSSOP package suits small-form-factor portable vibration analyzers, and the FIFO enables capture-and-burst to local memory for offline post-processing when the host is busy with operator-interface tasks.
おすすめ
Medical Multi-Channel Patient Monitoring
Patient-side instruments such as multi-lead ECG and EMG recorders require synchronized sampling of multiple bioelectric channels. The THS1206QDAR provides four simultaneously-sampled 12-bit channels at 6 MSPS aggregate, which can be time-divided across many leads for low-bandwidth bioelectric signals. The Q-grade -40 C to +125 C rating covers clinical environments and portable home-care devices alike. Pair the ADC with low-noise instrumentation amplifiers (e.g. INA128) on the front end, and decouple AVDD/DVDD carefully to maintain CMRR across all four channels.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: THS1206QDAR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | THS1206CDAR | THS1206IDA | THS1206QDA |
|---|---|---|---|---|
| Package | 32-TSSOP (DA) | 32-TSSOP (DA) - same | 32-TSSOP (DA) - same | 32-TSSOP (DA) - same |
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits |
| Sample Rate | 6 MSPS | 6 MSPS | 6 MSPS | 6 MSPS |
| Operating Temperature Range | -40 C to +125 C (Q-grade) | 0 C to +70 C (C-grade) | -40 C to +85 C (I-grade) | -40 C to +125 C (Q-grade) |
| Input Channels | 2 or 4 simultaneous | 2 or 4 simultaneous | 2 or 4 simultaneous | 2 or 4 simultaneous |
| Integral FIFO | 16 words | 16 words | 16 words | 16 words |
| Packaging Format | Tape & Reel | Tape & Reel | Tape & Reel | Tray |
主な差別化要因
- Widest industrial temperature grade within the THS1206 family （vs THS1206CDAR)
- Identical silicon to THS1206CDAR/IDATA, fully pin-compatible （vs THS1206IDA)
- Tape-and-reel packaging for high-volume SMT lines （vs THS1206QDA)
設計ノート
Separate the analog (AVDD/AGND) and digital (DVDD/DGND) supplies with a ferrite bead and decouple each AVDD pin with a 100 nF X7R ceramic placed within 5 mm of the pin. Keep the analog input traces short and matched between the positive and negative pairs to preserve common-mode rejection. The exposed thermal pad (if present on your PCB layout variant) should be soldered to a grounded copper pour to reduce thermal resistance and provide a low-impedance AGND return path.
Configure the FIFO threshold register to match the host DMA burst length - under-thresholded reads can cause FIFO overflow and silently lost samples. Always read the FIFO status register before initiating a burst transfer, and verify the auto-scan sequencer is disabled when only a single channel is needed to avoid phantom conversions on inactive inputs.
When driving the analog inputs from a high-impedance source, add an external buffer amplifier (such as the OPA2277) within 25 mm of the ADC pins to preserve THD and SNR. Source impedances above 1 kohm interact with the internal track-and-hold and degrade linearity. Place a small RC anti-aliasing filter (typically 10 ohm + 33 pF) at each input pair to limit out-of-band noise folding into the Nyquist band.
コンプライアンス情報
RoHS and lead-free per TI product page; AEC-Q100 not specifically advertised for this ADC - check latest TI datasheet for automotive qualification status.
