TLV5580IPWG4 - 8-Bit 80 MSPS Low-Power ADC | Texas Instruments
部品番号: TLV5580IPWG4 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $7.85 | $7.85 |
| 10 | $7.1 | $71.00 |
| 100 | $6.35 | $635.00 |
| 500 | $5.7 | $2,850.00 |
| 1,000 | $5.1 | $5,100.00 |
TLV5580IPWG4 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog waveform and produces a discrete binary code proportional to the input amplitude. The TLV5580 belongs to the pipelined ADC family, which sits in the hierarchy: ADC -> data converter -> data acquisition IC -> mixed-signal semiconductor. Pipelined ADCs use multiple low-resolution stages to achieve high sample rates at modest power, making them a standard choice for IF-sampling communications, CCD imaging, and digital oscilloscope front ends.
Key features of the TLV5580 include 80 MSPS maximum sampling rate, single 3.3 V supply operation, 3.3 V TTL/CMOS-compatible digital I/O that simplifies interface to modern FPGAs and ASICs, an internal bottom-plate reference that reduces external component count, and an adjustable reference input for gain trim. The 700 MHz analog input bandwidth supports undersampling architectures where the ADC digitizes IF frequencies well above Nyquist. The 28-TSSOP (PW) footprint is pin-compatible across the broader TLV/TLC ADC family from Texas Instruments.
Architecturally the device uses a multi-stage pipeline with internal sample-and-hold and digital error correction. The combination of 80 MSPS and 8-bit resolution keeps per-conversion power low (single-digit mA from a 3.3 V rail), which is the original design target: applications where the ADC must sit on the same board as noisy digital logic without dominating the power budget. The TLV5580 has been replaced by the ADS831 in TI's portfolio but remains specified and available for legacy designs.
Typical applications include CCD imaging digitizers, video capture front ends, IF-sampling communications receivers, portable battery-powered instrumentation, and digital oscilloscope input stages. In each case the part provides a compact, low-power, single-supply path from analog to digital.
When designing with the TLV5580, decouple AVDD and DVDD separately close to the package and follow standard pipelined-ADC layout practice: keep analog input traces short, use a ground plane under the analog input, and provide a clean 3.3 V rail. The PW suffix indicates tube packaging; the device is also offered in tape and reel as TLV5580IPWR.
ドロップイン代替品: TLV5580IPWG4 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: TLV5580IPWG4 （同一形状・フットプリント） — 相違点: Architecture, Operating Temperature, Package, Resolution.
クイック比較ツール — 並列比較する代替部品を選択:
ADS831IPWR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
ADS831IPW
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TLV5580IPWR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TLC5540IPWR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TLV2545IDGKR
✅ ドロップイン✓ 在庫あり
$2.33 / 個
データシートを見る →TLV5580IPWG4 最大定格＆電気的特性
| 分解能 | 8 bit |
| Number of Channels | 1 Input |
| Architecture | Pipelined |
| サンプリングレート | 80 MSPS |
| Analog Input Bandwidth | 700 MHz (typ) |
| 電源電圧 | 3.3 V single supply |
| Digital I/O Logic | 3.3 V TTL/CMOS-compatible |
| Data Interface | Parallel |
| Conversion Time | 0.0125 us (typ) |
| Reference | Internal top and bottom; adjustable reference input |
| 動作温度 | -40C to +85C (industrial) |
| パッケージ | 28-TSSOP (PW, 0.173 in / 4.40 mm width) |
| 実装タイプ | Surface Mount |
| Terminal Form | Gull Wing |
| Number of Terminals | 28 |
| Packaging | Tube (PW suffix); also offered in tape and reel (PWR) |
TLV5580IPWG4 ピン構成
| ピン 1 | AVDD — Analog supply voltage (3.3 V) |
| ピン 2 | AIN — Analog input |
| ピン 3 | AGND — Analog ground |
| ピン 4 | REFT — Reference top (internal) |
| ピン 5 | REFB — Reference bottom (internal) |
| ピン 6 | VREF — Reference adjust input |
| ピン 7 | AGND — Analog ground |
| ピン 8 | AVDD — Analog supply voltage (3.3 V) |
| ピン 9 | CLK — Clock input |
| ピン 10 | CLKB — Complementary clock input |
| ピン 11 | PD — Power-down control |
| ピン 12 | DVDD — Digital supply voltage (3.3 V) |
| ピン 13 | DGND — Digital ground |
| ピン 14 | D7 — Data output bit 7 (MSB) |
| ピン 15 | D6 — Data output bit 6 |
| ピン 16 | D5 — Data output bit 5 |
| ピン 17 | D4 — Data output bit 4 |
| ピン 18 | DVDD — Digital supply voltage (3.3 V) |
| ピン 19 | DGND — Digital ground |
| ピン 20 | D3 — Data output bit 3 |
| ピン 21 | D2 — Data output bit 2 |
| ピン 22 | D1 — Data output bit 1 |
| ピン 23 | D0 — Data output bit 0 (LSB) |
| ピン 24 | DGND — Digital ground |
| ピン 25 | DVDD — Digital supply voltage (3.3 V) |
| ピン 26 | OEB — Output enable (active low) |
| ピン 27 | AVDD — Analog supply voltage (3.3 V) |
| ピン 28 | AGND — Analog ground |
主な用途
TLV5580IPWG4 の用途: 6 件s: CCD Imaging Digitizer, Video Capture Front End, IF-Sampling Communications Receiver, Portable Battery-Powered Instrumentation, Digital Oscilloscope Input Stage, Industrial Process Control Data Acquisition.
CCD Imaging Digitizer
The TLV5580IPWG4 suits CCD imaging front ends where the analog pixel stream must be digitized at high speed for image reconstruction. Its 80 MSPS sample rate exceeds the pixel clock of VGA-resolution CCD cameras, while the 700 MHz analog input bandwidth preserves the fast edge transitions typical of CCD output stages. The 8-bit resolution matches the dynamic range of consumer CCD imagers, and the parallel 3.3 V CMOS outputs drive an FPGA image pipeline directly. Single 3.3 V operation simplifies power design in compact camera modules where space is at a premium.
おすすめ
Video Capture Front End
In video capture applications the TLV5580IPWG4 acts as the digitizer between a video amplifier and an FPGA-based scaler/encoder. The 80 MSPS sample rate supports standard-definition and EDTV video bandwidths, while the 8-bit resolution is sufficient for compressed video pipelines such as MPEG-2 and H.264 encode. The 700 MHz input bandwidth handles luma/chroma transitions cleanly, and the parallel output keeps latency low for real-time processing. Designers benefit from single 3.3 V supply operation that fits small-form-factor capture cards.
おすすめ
IF-Sampling Communications Receiver
The TLV5580IPWG4 enables IF-sampling receivers by digitizing intermediate-frequency signals in software-defined radio architectures. The 700 MHz analog input bandwidth allows the ADC to undersample IF frequencies well above Nyquist, while 80 MSPS captures the full IF bandwidth of common 2G/3G cellular and ISM-band signals. The 8-bit resolution is sufficient for envelope detection and AGC loops, and the parallel interface feeds an FPGA digital downconverter directly. Low single-supply power makes the part attractive for portable SDR hardware.
おすすめ
Portable Battery-Powered Instrumentation
The TLV5580IPWG4 fits battery-powered test instruments where power budget, board area, and single-supply operation dominate the design trade-off. Its low mA-class consumption at 80 MSPS preserves battery life in handheld oscilloscopes and field-portable data loggers. The 700 MHz input bandwidth covers signals beyond audio into video and IF ranges, while the parallel 3.3 V outputs integrate with low-power FPGAs without level shifters. Industrial -40C to +85C rating supports outdoor and industrial deployments.
おすすめ
Digital Oscilloscope Input Stage
In low-bandwidth digital oscilloscopes the TLV5580IPWG4 serves as the digitizer after the front-end attenuator and amplifier chain. Its 80 MSPS real-time sample rate captures repetitive waveforms up to tens of MHz with equivalent-time reconstruction, and the 700 MHz analog input bandwidth preserves fast edge fidelity. The 8-bit resolution is consistent with cost-optimized scope designs, and the parallel CMOS outputs feed a memory buffer FPGA in real time. Single 3.3 V supply simplifies thermal and power design in compact handheld scopes.
おすすめ
Industrial Process Control Data Acquisition
Industrial data-acquisition boards use the TLV5580IPWG4 to digitize fast analog control loops such as vibration, sonar, and ultrasonic sensors. The 80 MSPS sample rate exceeds the bandwidth of mechanical vibration signals, while the 700 MHz input bandwidth handles ultrasonic transducer outputs cleanly. The industrial -40C to +85C rating covers factory floor and outdoor cabinet environments, and the 3.3 V CMOS outputs interface directly to industrial FPGAs. The 28-TSSOP footprint supports high-density multi-channel DAQ boards.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: TLV5580IPWG4 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | ADS831IPWR | ADS831IPW | TLV5580IPWR | TLC5540IPWR | TLV2545IDGKR |
|---|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | 28-TSSOP (PW) | 28-TSSOP (PW) - same | 28-TSSOP (PW) - same | 28-TSSOP (PW) - same | 28-TSSOP (PW) - same | 28-TSSOP (DGK) - same TSSOP-28 family |
| Resolution | 8 bit | 8 bit | 8 bit | 8 bit | 8 bit | 12 bit |
| Sample Rate | 80 MSPS | 80 MSPS | 80 MSPS | 80 MSPS | 40 MSPS | 200 kSPS |
| Architecture | Pipelined | Pipelined | Pipelined | Pipelined | Pipelined | SAR |
| Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| Supply Voltage | 3.3 V single | 3.3 V single | 3.3 V single | 3.3 V single | 5 V single | 2.7-5.5 V |
| Data Interface | Parallel | Parallel | Parallel | Parallel | Parallel | Serial SPI |
| Lifecycle Status | NRND | Active | Active | NRND | NRND | Active |
主な差別化要因
- TI-specified ADS831 drop-in replacement available with active lifecycle （vs ADS831IPWR)
- 700 MHz analog input bandwidth supports undersampling （vs TLV2545IDGKR)
- Higher sample rate than slower TI ADC family members （vs TLC5540IPWR)
設計ノート
Estimated: the TLV5580IPWG4 specifies a single 3.3 V supply but separates analog (AVDD) and digital (DVDD) domains internally. Place a ferrite bead or small resistor between AVDD and DVDD supplies, and decouple each pin with a 0.1 uF ceramic capacitor as close to the package as possible. Add a bulk 10 uF tantalum or ceramic capacitor near the supply entry to handle transient current demand at 80 MSPS. Keep analog and digital grounds joined at a single star point under the IC.
Estimated: the pipelined ADC has 700 MHz analog input bandwidth and is sensitive to clock jitter on CLK and to digital output noise coupling into AVDD. Route the clock trace as a short, controlled-impedance line, and shield it from the analog input trace. Use a continuous ground plane under the analog input network and avoid routing digital outputs (D0-D7) directly under the analog input pin. Maintain 50 ohm characteristic impedance on the analog input trace to preserve 700 MHz bandwidth.
The TLV5580IPWG4 uses a parallel 3.3 V CMOS output bus that switches up to 80 million times per second. Each transition draws brief current spikes that can couple into the analog supply. Use output series resistors (22-33 ohm) close to the digital outputs to dampen ringing, and keep output trace lengths matched within 1-2 cm to avoid skew. Consider an external output buffer if driving long traces or many loads.
Do not exceed the absolute maximum analog input voltage range; overdrive at AIN can permanently damage the input protection structure. Make sure the CLK input is clean - jitter on the clock translates directly into SNR degradation. Verify the reference voltage setting (VREF pin) before sampling - an incorrect reference causes systematic gain error. The TLV5580 is NRND, so for new designs the TI-recommended ADS831 pin-compatible replacement should be used instead.
コンプライアンス情報
Pb-free 28-TSSOP package; RoHS/REACH compliant per Texas Instruments product declaration. Not AEC-Q100 qualified - for automotive applications consider AEC-Q100 qualified alternatives from the TI ADC portfolio.
