TPS544C20RVFR - 30A 18V Sync Buck Converter | Texas Instruments
部品番号: TPS544C20RVFR ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.2 | $9.20 |
| 10 | $8.28 | $82.80 |
| 100 | $7.36 | $736.00 |
| 500 | $6.62 | $3,310.00 |
| 1,000 | $5.88 | $5,880.00 |
| 3,000 | $5.21 | $15,630.00 |
TPS544C20RVFR 概要
A buck converter (step-down switching regulator) is a DC-DC converter that produces a lower DC output voltage from a higher DC input, using a controlled MOSFET switch, an inductor, and a capacitor. The TPS544C20 belongs to the broader synchronous buck controller family (SWIFT) and within the non-isolated point-of-load (POL) converter hierarchy, used to feed downstream processors, ASICs, and memory rails from a single intermediate bus.
Key features include D-CAP and D-CAP2 mode selection for ceramic-cap output, lossless low-side MOSFET current sensing, 600-mV reference with 0.5% accuracy, integrated bootstrap switch, and PMBus-programmable output voltage, soft-start, and fault telemetry. Selectable switching frequency, current limit, and fault responses via PMBus simplify multi-rail digital infrastructure design.
Typical applications include server and storage POL rails, FPGA/DSP/processor core and I/O supplies, networking ASICs, and high-current distributed bus architectures in telecom and datacom. The 0.5% reference and D-CAP2 mode let designers meet tight DC tolerance and fast transient requirements with all-ceramic output capacitors.
When designing with this device, use the recommended PowerPAD footprint and provide a sufficient thermal copper pour. Configure PMBus registers in production firmware and respect the absolute-maximum VIN of 22 V; an input TVS is recommended for transient protection in harsh environments.
ドロップイン代替品: TPS544C20RVFR — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: TPS544C20RVFR （同一形状・フットプリント） — 相違点: Digital Interface, Package, Mounting Type, Output Voltage Range, Topology.
クイック比較ツール — 並列比較する代替部品を選択:
TPS544B20RVFR
✅ ドロップイン✓ 在庫あり
$5.1 / 個
データシートを見る →TPS544C25RVFT
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TPS544C20RVF
✅ ドロップイン✓ 在庫あり
$8.1 / 個
データシートを見る →TPS544C21RVFR
✅ ドロップイン📋 参考代替品（カタログ未掲載）
TPS544C20RVFR 最大定格＆電気的特性
| 機能 | Synchronous Buck Converter (Step-Down) |
| 入力電圧範囲 | 4.5 V to 18 V |
| 出力電圧範囲 | 0.6 V to 5.5 V |
| 最大出力電流 | 30 A |
| 基準電圧 | 0.6 V (0.5% accuracy) |
| High-Side Rds(on) | 4.5 mΩ (typical, stacked NexFET) |
| Low-Side Rds(on) | 2.0 mΩ (typical, stacked NexFET) |
| Control Mode | D-CAP / D-CAP2 selectable |
| Current Sensing | Lossless low-side MOSFET sensing |
| Digital Interface | PMBus |
| パッケージ | LQFN-CLIP-40 (RVF) 5 mm x 7 mm |
| 実装タイプ | Surface Mount (PowerPAD/thermal pad) |
| 出力数 | 1 |
| トポロジー | Synchronous buck (integrated FETs) |
| 出力構成 | Positive, adjustable |
| 動作温度 | -40C to +125C (junction) |
| RoHS ステータス | Compliant |
TPS544C20RVFR ピン構成
| ピン 1 | PGND — Power ground for low-side FET |
| ピン 2 | VIN — Input supply voltage |
| ピン 3 | VIN — Input supply voltage |
| ピン 4 | VREG — Internal regulator bypass/decoupling |
| ピン 5 | EN/UVLO — Enable / undervoltage lockout |
| ピン 6 | MODE — D-CAP / D-CAP2 selection |
| ピン 7 | VSEL — Voltage selection / PMBus address strap |
| ピン 8 | SCL — PMBus serial clock |
| ピン 9 | SDA — PMBus serial data |
| ピン 10 | ALERT — PMBus alert (open-drain) |
| ピン 11 | PGOOD — Power-good output (open-drain) |
| ピン 12 | VOUT_SNS — Output voltage sense input |
| ピン 13 | VSENSE — Differential VOUT remote sense |
| ピン 14 | VSENSE_RTN — Differential VOUT sense return |
| ピン 15 | RT/SS — Switching frequency / soft-start set |
| ピン 16 | COMP — Compensation node (loop) |
| ピン 17 | ILIM — Current limit set resistor |
| ピン 18 | OCP — Over-current protection trim |
| ピン 19 | BOOT — Bootstrap capacitor for HS FET |
| ピン 20 | SW — Switch node (HS FET drain) |
| ピン 21 | SW — Switch node |
| ピン 22 | SW — Switch node |
| ピン 23 | SW — Switch node |
| ピン 24 | PGND — Power ground |
| ピン 25 | PGND — Power ground |
| ピン 26 | AGND — Analog / signal ground |
| ピン 27 | BST — Bootstrap return pin |
| ピン 28 | VCC — Internal 5-V LDO bypass |
| ピン 29 | REF — 0.6 V reference bypass |
| ピン 30 | MODE/SYNC — Mode or sync per variant |
| ピン 31 | DNC — Do not connect (per datasheet) |
| ピン 32 | DNC — Do not connect (per datasheet) |
| ピン 33 | DNC — Do not connect (per datasheet) |
| ピン 34 | DNC — Do not connect (per datasheet) |
| ピン 35 | DNC — Do not connect (per datasheet) |
| ピン 36 | DNC — Do not connect (per datasheet) |
| ピン 37 | VIN — Input supply voltage |
| ピン 38 | VIN — Input supply voltage |
| ピン 39 | PGND — Power ground |
| ピン 40 | PGND — Power ground / thermal pad |
主な用途
TPS544C20RVFR の用途: 6 件s: Server / Storage Point-of-Load, FPGA / DSP / Processor Core Supply, Networking ASIC and Switch Power, Industrial 24-V Distributed Bus POL, Datacenter / Telecom Board POL, Test & Measurement Equipment POL.
Server / Storage Point-of-Load
The TPS544C20RVFR delivers a tightly regulated 1.0-V to 3.3-V rail at up to 30 A for server CPUs, memory buffers, and storage ASICs from a 12-V intermediate bus. Its D-CAP2 control with 4.5 mΩ / 2.0 mΩ NexFETs sustains step-load transients of 10 A/us, vital in multi-rail server boards. PMBus telemetry (VOUT, IOUT, temperature) enables real-time platform management. Compared with a 12-V-input analog buck, it cuts BOM cost by removing external FETs and current-sense resistors. Mount on the recommended PowerPAD footprint and follow the layout in the TI datasheet for best thermal performance.
おすすめ
FPGA / DSP / Processor Core Supply
The TPS544C20RVFR provides 30 A at 0.85 V - 1.2 V for high-performance FPGA and DSP cores that demand fast load-step response. The internal 0.5%-accurate reference keeps DC tolerance inside the FPGA's core-rail specification, and D-CAP2 control eliminates the need for external compensation networks. The 5 mm x 7 mm LQFN-CLIP package and integrated NexFETs shrink the POL footprint, freeing board area for high-density I/O. For multi-core processors requiring telemetry, PMBus gives designers visibility into VOUT drift and junction temperature.
おすすめ
Networking ASIC and Switch Power
The TPS544C20RVFR feeds high-current switching ASICs and packet processors in Ethernet switches and routers. With 4.5-V-to-18-V input and 30-A output it covers 5-V, 9-V and 12-V distribution buses commonly used in telecom and datacom. PMBus enables per-port voltage margining during factory test for ATE-style validation. Lossless low-side MOSFET current sensing removes the external shunt, simplifying board layout in dense line-card designs. Use the TI TPS544C20 datasheet layout guidelines to keep switching noise away from sensitive clock-recovery PLLs.
おすすめ
Industrial 24-V Distributed Bus POL
In industrial 24-V nominal bus systems, the TPS544C20RVFR derives 5-V, 3.3-V or 1.8-V rails with up to 30 A. Its 18-V absolute maximum is well below 24 V, so designers add an upstream protection FET/TVS (e.g. TPS25942) to drop input transients. The -40 C to +125 C junction rating supports outdoor enclosures and factory automation. PMBus programmability means the same hardware platform can support multiple output voltages via firmware - reducing SKUs in factory-automation product families.
おすすめ
Datacenter / Telecom Board POL
The TPS544C20RVFR supports 5G base stations and cloud datacenter boards that draw power from 12-V intermediate bus. Its 5x7 mm LQFN-CLIP footprint with PowerPAD achieves about 19 C/W junction-to-board, supporting full 30-A at 1 V out from 12 V in within thermal limits. PMBus telemetry aligns with PSMI / Intel VR13 telemetry conventions used in hyperscale datacenters. The 1.2-mm maximum height fits 1U/2U server-card mechanical envelopes; design teams can reuse one PCB across multiple voltage variants by reprogramming the PMBus command set.
おすすめ
Test & Measurement Equipment POL
The TPS544C20RVFR serves as the low-ripple, high-current rail powering FPGAs, ADCs, and DACs inside test and measurement platforms. Output noise stays low thanks to D-CAP2 hysteretic control, while PMBus lets engineers adjust rail voltage on the fly during characterization. The 0.5% reference accuracy supports calibration-grade analog instruments where DC accuracy is mission-critical. For high-precision TI ADC reference chains, place the TPS544C20 upstream of a lower-noise LDO (e.g. TPS7A47) to combine 30-A delivery with sub-5 uVrms final noise.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: TPS544C20RVFR — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | TPS544B20RVFR | TPS544C25RVFT | TPS544C20RVF | TPS544C21RVFR |
|---|---|---|---|---|---|
| Brand | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments | Texas Instruments |
| Package | LQFN-CLIP-40 (RVF) 5x7 mm | LQFN-CLIP-40 (RVF) 5x7 mm - same | LQFN-CLIP-40 (RVF) 5x7 mm - same | LQFN-CLIP-40 (RVF) 5x7 mm - same | LQFN-CLIP-40 (RVF) 5x7 mm - same |
| Maximum Output Current | 30 A | 20 A | 30 A | 30 A | 30 A |
| Input Voltage Range | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V | 4.5 V to 18 V |
| Output Voltage Range | 0.6 V to 5.5 V | 0.6 V to 5.5 V | 0.5 V to 5.5 V | 0.6 V to 5.5 V | 0.6 V to 5.5 V |
| Control Mode | D-CAP / D-CAP2 | D-CAP / D-CAP2 | D-CAP2 (SYNC/RESET_B) | D-CAP / D-CAP2 | D-CAP / D-CAP2 |
| Pin 30 Function | MODE | MODE | SYNC / RESET_B (dual function) | MODE | MODE |
| PMBus Support | Yes | Yes | Yes | Yes | Yes |
主な差別化要因
- Highest pin-compatible 30-A current option in 5x7 LQFN-CLIP family （vs TPS544B20RVFR)
- Pin-30 stays as MODE, not repurposed as SYNC/RESET_B （vs TPS544C25RVFT)
- Integrated 4.5 mΩ / 2.0 mΩ NexFET power stage （vs TPS543820RPYR)
設計ノート
Use the recommended TI PowerPAD footprint and stitch the AGND/PGND planes with at least 8 vias under the thermal pad to keep junction temperature acceptable at 30 A. Place input ceramic capacitors (2x 22 uF / 25 V) within 2 mm of the VIN pins to suppress switching spikes and minimize the SW-node copper area to reduce EMI. Estimated thermal resistance with the recommended footprint is ~19 C/W; at 12 V in / 1.0 V out / 30 A, dissipation is ~3.3 W and a junction rise of ~63 C above board is expected - derate at high ambient.
At full 30 A from 12 V to 1.0 V the converter dissipates roughly 11 W (top-of-board minus output) plus 4 mΩ losses - observed datasheet case thermal resistance theta_JC of ~1.5 C/W combined with ~19 C/W theta_JB yields a junction rise of ~190 C, which is over the absolute limit. Always check both theta_JB and full-power dissipation in your specific board, and respect maximum-output-current derating curves from -40 C to +125 C.
Pin 30 is repurposed between TPS544C20 (MODE) and TPS544C25 (SYNC/RESET_B); verify the BOM and the schematic carefully before substituting. The MODE strap on TPS544C20 should never be left floating - use a 100 kΩ pull-up or pull-down to set D-CAP2 vs D-CAP explicitly. The PMBus address is set by external resistors on VSEL; collisions on a shared PMBus segment will block all digital communication.
Route the SW (switch) copper trace on the top layer only and keep it tight to minimize radiated noise. Place bootstrap capacitor between BOOT and SW within 2 mm of those pins. Place the VOUT differential sense pair next to the load to overcome IR drops across the output power path. Use a 4-layer stack with a solid GND plane beneath the SW and inductor copper pour. Failure to follow these rules can produce sub-harmonic oscillation, ringing, or PMBus noise coupling.
コンプライアンス情報
Per TI product page: RoHS compliant, Pb-free reflow profile per JEDEC J-STD-020, halogen-free mold compound. Not AEC-Q100 qualified; use TPS544C20-Q1 part variant for automotive designs. Data sourced from TI.com/datasheet distributor pages.
