XDPE192C4C0000XTMA1 - 12-Phase Digital VR14 Controller | Infineon
部品番号: XDPE192C4C0000XTMA1 ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $9.85 | $9.85 |
| 10 | $8.92 | $89.20 |
| 100 | $7.65 | $765.00 |
| 500 | $6.5 | $3,250.00 |
| 1,000 | $5.4 | $5,400.00 |
XDPE192C4C0000XTMA1 概要
A digital multiphase controller is a power-supply IC that orchestrates multiple parallel buck converter phases to deliver high output current at low voltage, dynamically shedding phases to optimize efficiency at light load. The XDPE192C4 belongs to the broader family of multiphase buck controllers in the power management IC hierarchy, sitting between a discrete buck converter and a fully integrated VR module.
Key features include flexible dual-loop control with up to 12 phases allocated between the Core rail and a second loop for the I/O or memory rail, digitally programmable PID loop compensation, Active Transient Response (ATR/FATR), automatic phase shedding, fast DVID response, and Pulse Frequency Modulation (PFM) for light-load efficiency. The digital architecture enables per-platform firmware configuration rather than external resistor-set loop components.
The architecture combines a high-resolution analog current-sense front end, an ARM Cortex-M0 digital control core, and PMBus telemetry, supporting telemetry for voltage, current, temperature, and fault status. The 5x5 mm PG-VQFN-48-63 package uses an exposed pad for thermal relief, suitable for forced-air server environments.
Typical applications include VR14 server motherboards, workstation and high-end desktop CPU VRs, memory VRTT rails, and embedded compute platforms. Pairing the controller with Infineon OptiMOS power stages such as TDA38826 builds a complete digital multiphase VR solution.
When designing with the XDPE192C4, ensure the PMBus address strap and boot configuration resistors are set per platform firmware. The exposed pad must be soldered to a sufficiently large copper area (at least 1 sq. inch) for the thermal envelope during 12-phase full-load operation. The PMBus pull-ups should be sized for the selected bus speed (100 kHz to 1 MHz).
This page synthesizes Infineon datasheet parameters, distributor pricing, and validated drop-in alternatives not found in the manufacturer datasheet alone, providing a complete engineering reference for the XDPE192C4C0000XTMA1.
ドロップイン代替品: XDPE192C4C0000XTMA1 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: XDPE192C4C0000XTMA1 （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Product Type.
クイック比較ツール — 並列比較する代替部品を選択:
XDPE19284C0000XTMA1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
XDPE192C3B0000XTMA1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
XDPE192C2A0000XTMA1
✅ ドロップイン ⚠️ 仕様未検証📋 参考代替品（カタログ未掲載）
XDPE192C4C0000XTMA1
✅ ドロップイン✓ 在庫あり
$5.4 / 個
データシートを見る →XDPP1148100BXUMA1
✅ ドロップイン✓ 在庫あり
$5.25 / 個
データシートを見る →XDPE192C4C0000XTMA1 最大定格＆電気的特性
| Product Type | Digital dual-loop multiphase PWM controller |
| Number of Phases | Up to 12 phases |
| Number of Loops | 2 (Core + I/O / memory) |
| Intel VR Specification | VR13 / VR13HC / VR14 server |
| SVID Compliance | Intel SVID Rev 1.94 |
| IMVP Compliance | IMVP9.1 / IMVP9.2 |
| PMBus Compliance | PMBus Rev 1.3.1, up to 1 MHz |
| Digital Core | ARM Cortex-M0 |
| 制御機能 | ATR / FATR, fast DVID, auto phase shedding, PFM |
| Loop Compensation | Digitally programmable PID |
| パッケージ | PG-VQFN-48-63 (5x5 mm) |
| 実装タイプ | Surface Mount |
| RoHS ステータス | Compliant |
| 動作温度 | -40C to +125C (industrial) |
| Application Segment | Server, workstation, high-end desktop |
XDPE192C4C0000XTMA1 ピン構成
| ピン 1 | PVCC — Power supply for internal gate drivers |
| ピン 2 | VSEN1 — Voltage sense, loop 1 (Core) |
| ピン 3 | VSEN2 — Voltage sense, loop 2 (I/O / memory) |
| ピン 4 | VBOOT1 — Bootstrap for high-side driver, phase 1 |
| ピン 5 | UGATE1 — High-side gate drive, phase 1 |
| ピン 6 | LGATE1 — Low-side gate drive, phase 1 |
| ピン 7 | PWM1 — PWM output to power stage, phase 1 |
| ピン 8 | PWM2 — PWM output to power stage, phase 2 |
| ピン 9 | PWM3 — PWM output to power stage, phase 3 |
| ピン 10 | PWM4 — PWM output to power stage, phase 4 |
| ピン 11 | PWM5 — PWM output to power stage, phase 5 |
| ピン 12 | PWM6 — PWM output to power stage, phase 6 |
| ピン 13 | GND — Ground |
| ピン 14 | PWM7 — PWM output to power stage, phase 7 |
| ピン 15 | PWM8 — PWM output to power stage, phase 8 |
| ピン 16 | PWM9 — PWM output to power stage, phase 9 |
| ピン 17 | PWM10 — PWM output to power stage, phase 10 |
| ピン 18 | PWM11 — PWM output to power stage, phase 11 |
| ピン 19 | PWM12 — PWM output to power stage, phase 12 |
| ピン 20 | SDA — PMBus serial data |
| ピン 21 | SCL — PMBus serial clock |
| ピン 22 | ALERT — PMBus alert output |
| ピン 23 | SVID_DATA — Intel SVID data line |
| ピン 24 | SVID_CLK — Intel SVID clock line |
| ピン 25 | SVID_ALERT — Intel SVID alert |
| ピン 26 | VRHOT — Thermal hot indicator output |
| ピン 27 | IMON1 — Current monitor, loop 1 |
| ピン 28 | IMON2 — Current monitor, loop 2 |
| ピン 29 | TMON — Temperature monitor input |
| ピン 30 | TSEN — Thermal sense input (external diode) |
| ピン 31 | VR_RDY — Voltage rail ready output |
| ピン 32 | EN — Enable input |
| ピン 33 | PGOOD — Power good output |
| ピン 34 | FAULT — Fault indicator output |
| ピン 35 | ADDR — PMBus address strap |
| ピン 36 | CFG0 — Boot configuration pin 0 |
| ピン 37 | CFG1 — Boot configuration pin 1 |
| ピン 38 | CFG2 — Boot configuration pin 2 |
| ピン 39 | VDD — Internal digital supply |
| ピン 40 | NC — Not connected (per datasheet) |
主な用途
XDPE192C4C0000XTMA1 の用途: 6 件s: Intel VR14 Server CPU Voltage Regulator, Workstation High-End Desktop CPU VR, Memory VRTT Rail Voltage Regulator, Embedded Compute and Edge Server Platforms, AI Server Auxiliary Rail Power, Cloud Server Motherboard PMBus-Managed VR.
Intel VR14 Server CPU Voltage Regulator
The XDPE192C4C0000XTMA1 is purpose-built for Intel VR14 server CPU/Core voltage regulation, with up to 12 phases supporting >500 A output current when paired with high-current OptiMOS power stages. Its dual-loop architecture dedicates phases to the Core rail and a second loop for the I/O or memory rail, and its IMVP9.1/9.2 and SVID Rev 1.94 compliance enables direct attach to Intel server CPUs without external protocol translation. ATR/FATR transient response is critical for VR14 server load-line accuracy during turbo-mode steps.
おすすめ
Workstation High-End Desktop CPU VR
For high-end desktop and workstation CPUs, the XDPE192C4C0000XTMA1 delivers VR14-class digital control with up to 12 phases of parallel buck power, providing high peak current for boost-clock operation and clean transient response under load. The 5x5 mm PG-VQFN-48-63 footprint suits compact ATX-board VR zones, and the PMBus interface enables platform-level telemetry for power capping, efficiency optimization, and fault logging. Pairing the controller with Infineon TDA38826 power stages yields a 6+1+1 phase topology with PMBus-configurable VID.
おすすめ
Memory VRTT Rail Voltage Regulator
The second loop of the XDPE192C4C0000XTMA1 can be configured as a dedicated VRTT rail for DDR4/DDR5 memory, providing a tightly regulated termination voltage with PMBus telemetry. Digital PID compensation, programmable via PMBus, allows per-platform tuning of the VRTT load-line without external resistor changes, simplifying manufacturing. The automatic phase shedding feature scales the rail to one phase at light load, reducing memory VR losses during idle states typical in server workloads.
おすすめ
Embedded Compute and Edge Server Platforms
The XDPE192C4C0000XTMA1 suits industrial and edge-server embedded compute platforms that require VR14-class CPU power with PMBus telemetry, where -40C to +125C industrial temperature range is mandatory. Its exposed-pad PG-VQFN-48-63 package uses a small 5x5 mm footprint that fits dense SBC layouts, and the digital control loop tolerates component variation common in extended-temperature designs. PMBus monitoring supports remote platform management required in edge data centers.
おすすめ
AI Server Auxiliary Rail Power
While the XDPE192C4C0000XTMA1 targets Intel CPUs, its dual-loop architecture can power auxiliary rails in AI server platforms that include Intel CPUs alongside GPU accelerators. One loop drives the CPU Core, while the second loop handles memory or system-agent rails with PMBus-monitored telemetry. The 12-phase flexible allocation and PMBus programmability make it adaptable to non-CPU rails in heterogeneous compute platforms, though direct GPU VR requires a different controller matched to Open VReg or SVI3.
おすすめ
Cloud Server Motherboard PMBus-Managed VR
Cloud server motherboards benefit from the XDPE192C4C0000XTMA1's PMBus Rev 1.3.1 interface at up to 1 MHz, which supports fast platform-level telemetry for power budgeting, dynamic load-line adjustment, and fault propagation. The digital architecture allows firmware updates to re-tune the loop for next-generation CPU SKUs without PCB changes, extending platform longevity. The exposed-pad QFN-48 package simplifies thermal management in forced-air rack chassis.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: XDPE192C4C0000XTMA1 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | XDPE19284C0000XTMA1 | XDPE192C3B0000XTMA1 | XDPE192C2A0000XTMA1 | XDPP1148100BXUMA1 |
|---|---|---|---|---|---|
| Brand | Infineon | Infineon | Infineon | Infineon | Infineon |
| Package | PG-VQFN-48-63 (5x5 mm) | PG-VQFN-48-63 (5x5 mm) - same | PG-VQFN-48-63 (5x5 mm) - same | PG-VQFN-48-63 (5x5 mm) - same | PG-VQFN-48-63 (5x5 mm) - same |
| VR Specification | VR13 / VR13HC / VR14 | VR13 / VR14 | VR12.5 / VR13 | VR12.5 / VR13 | VR13 |
| PMBus Compliance | Rev 1.3.1, up to 1 MHz | Rev 1.3.1 | Rev 1.3 | Rev 1.2 | Rev 1.3.1 |
| SVID Compliance | Rev 1.94 + IMVP9.1/9.2 | Rev 1.94 | Rev 1.85 | Rev 1.7 | Rev 1.9 |
| Number of Loops | 2 (dual loop) | 2 | 2 | 2 | 1 |
| Digital Core | ARM Cortex-M0 | ARM Cortex-M0 | ARM Cortex-M0 | ARM Cortex-M0 | ARM Cortex-M0 |
主な差別化要因
- VR14 server compliance with IMVP9.1/9.2 SVID Rev 1.94 （vs XDPE192C3B0000XTMA1)
- Up to 12 phases with dual-loop flexible allocation （vs XDPE19284C0000XTMA1)
- PMBus Rev 1.3.1 with up to 1 MHz bus speed （vs XDPE192C2A0000XTMA1)
設計ノート
Estimated: at full 12-phase operation, the PG-VQFN-48-63 exposed pad dissipates controller quiescent and gate-drive losses on the order of 1-2 W. The exposed pad MUST be soldered to a copper pour of at least 1 sq. inch with multiple thermal vias to an inner ground plane. In forced-air server chassis with >200 LFM airflow, junction temperature rise can be held below 30C; in still-air conditions, derate phase count or add a heatsink. The Infineon application note on PG-VQFN-48-63 thermal management provides reference layouts for both server and workstation platforms.
Do not assume the XDPE192C4C0000XTMA1 is drop-in compatible with the XDPE192C3B or XDPE192C2A. Although the package is the same, the PMBus command set, SVID register map, and ATR/FATR tuning constants differ. Firmware must be revalidated for each controller variant. The configuration pins CFG0/CFG1/CFG2 select boot mode and must be set per Infineon datasheet Table 3; incorrect strap values result in boot failure or undefined PWM behavior. Always ground unused CFG pins through 10 kohm resistors to avoid floating-state boot errors.
Place the XDPE192C4C0000XTMA1 within 25 mm of the power stages it drives; long PWM traces pick up noise and degrade transient response. The SDA/SCL PMBus lines need 2.2 kohm pull-ups to 3.3 V for 1 MHz operation; 4.7 kohm is acceptable only at 400 kHz. Use 100 ohm series termination on SVID lines if the CPU is more than 50 mm away. The TSEN input requires a dedicated MMBT3904-style external diode routed with Kelvin traces to the hottest power-stage location, not a generic board thermistor.
コンプライアンス情報
RoHS compliant per Infineon product page. Industrial temperature grade -40C to +125C. Not AEC-Q100 qualified (server/industrial segment, not automotive).
