FPGA & CPLD
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EPM5128GM/883 - 128-Macrocell MAX 5000 CPLD | Altera | Military
The Intel / Altera EPM5128GM/883 is a 128-macrocell high-density erasable programmable logic device (EPLD) from the classic MAX 5000 family, qualified to MIL-STD-883 Class B for military and aerospace applications. It provides 128 macrocells and up to 100 user I/O, an industry-leading density at introduction, packaged in a ceramic Pin-Grid Array (PGA) form factor with 192 pins per the verified Altera datasheet family. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that uses a sum-of-products architecture with a global interconnect fabric to implement combinational and sequential logic. CPLDs sit in the hierarchy between simple PLDs (PALs/GALs) and SRAM-based FPGAs, providing deterministic timing, instant-on configuration from on-chip EPROM cells, and high fan-in macrocell structures. The MAX 5000 family was one of Altera's first high-density erasable CPLD lines, built on a UV-erasable CMOS EPROM process that allowed field re-programming via windowed ceramic packages. Key features of the EPM5128GM/883 include 128 macrocells with up to 5,000 usable gates, 100% factory-tested operation over the military -55C to +125C temperature range, JTAG-compliant boundary-scan test support, and programmable power management with macrocell-level clock-enable control. The 192-pin ceramic PGA package provides mechanical robustness for high-shock and high-vibration environments typical of avionics and defense electronics. Architecturally, the EPM5128GM/883 uses Altera's classic Logic Array Block (LAB) and Programmable Interconnect Array (PIA) structure, with each macrocell containing a programmable AND/OR array feeding a configurable flip-flop. Configuration data is stored in on-chip EPROM cells, enabling the part to retain its logic pattern without external memory and to be re-programmed after UV erasure through the ceramic windowed package. Typical applications include military avionics bus interfaces, radar signal preprocessing, missile guidance logic, naval combat-system glue logic, and space-grade digital control. The combination of high density, MIL-STD-883 screening, and non-volatile EPROM configuration makes the EPM5128GM/883 particularly suited to long-lifecycle defense programs where component stability and traceability outweigh the need for state-of-the-art density. Designers should note that the EPM5128GM/883 uses 5 V TTL-compatible I/O and requires a +12 V VPP programming supply during device programming; the 192-pin PGA footprint requires through-hole PCB assembly, which impacts board density and assembly cost compared to surface-mount equivalents. This page synthesizes distributor pricing, MIL-STD-883 screening details, and drop-in / same-family alternatives that go beyond what the manufacturer datasheet alone provides for legacy defense procurement.
EPM5128GM/883B - Military MAX 5000 EPLD 128 Macrocell | Altera
The Altera EPM5128GM/883B is a 128-macrocell high-density, high-speed CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, supplied in a ceramic Pin Grid Array (PGA) package and screened to MIL-STD-883 Class B for defense and aerospace applications. It provides 100% factory-tested replacements for 7400-series SSI/MSI TTL and CMOS logic while integrating up to 100 equivalent PAL/GAL devices into a single package. The device operates over the military -55C to +125C temperature range and is offered as a user-configurable, high-performance Multiple Array Matrix architecture device. What is an EPLD? An EPLD (Erasable Programmable Logic Device) is a non-volatile, electrically erasable CMOS logic device that combines the integration density of gate arrays with the design flexibility of programmable logic. The MAX 5000 family sits in the hierarchy of programmable logic devices (EPLD -> PLD -> programmable logic -> digital IC -> semiconductor), bridging the gap between early PAL/GAL parts and modern FPGAs/CPLDs. EPLDs retain their configuration in on-chip non-volatile memory and require no external boot PROM, which is why they remain attractive for military and avionics applications. Key features of the EPM5128GM/883B include 128 macrocells, 16 dedicated inputs, and a propagation delay in the nanosecond range suited for high-speed bus decoding and state-machine replacement. The MAX 5000 Multiple Array Matrix (MAX) architecture combines the flexibility of macrocell-based logic with predictable, pin-locked timing - a critical property for synchronous military systems where routing-induced delay skew is unacceptable. The part is windowed ceramic and field-programmable through standard Altera programming hardware. Typical applications include military and avionics bus interface logic (1553B, ARINC 429 glue logic), radar signal pre-processing, sonar systems, missile guidance electronics, nuclear-hardened control systems, and any high-reliability design that previously relied on racks of 7400-series TTL. The MIL-STD-883B screening guarantees performance under vibration, thermal cycling, and extended temperature exposure. When designing with the EPM5128GM/883B, engineers must provide a socket for the ceramic PGA or use a compatible adapter footprint, and program the device using legacy Altera programming tools such as MAX+PLUS II. The /883B suffix indicates full Class B processing - if your system only needs industrial temperature ranges, the commercial EPM5128GM may suffice at lower cost.
EPM5128GM883B - 128-Macrocell UV EPLD MAX 5000 | Altera
The Altera EPM5128GM883B is a UV-erasable programmable logic device (EPLD) from the MAX 5000 family, featuring 128 macrocells, 52 I/O lines, 7 dedicated inputs, and a propagation delay of 55 ns, housed in a ceramic PGA-883 package and qualified to MIL-STD-883 Class B. The device is organized as 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), supports one external clock input, and operates from a single 5 V supply using CMOS technology. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic IC that combines AND/OR array logic with macrocell flip-flops. EPLDs sit at the bottom of the programmable logic hierarchy: macrocell -> CPLD -> programmable logic -> digital IC. Unlike SRAM-based FPGAs that require a configuration ROM, EPLDs retain their logic on power-down and boot in microseconds, which is critical for power-on control logic and glue logic replacement. Key features of the EPM5128GM883B include 128 macrocells of user logic, 59 total inputs (52 user I/O + 7 dedicated), 8 LABs, a PIA that distributes signals between every LAB with uniform delay, and 55 ns pin-to-pin propagation delay. The MAX 5000 architecture provides predictable timing because every signal path traverses the same PIA, simplifying static timing analysis versus SRAM FPGA fabric. Technically, the EPM5128GM883B uses UV-erasable EPROM cells for configuration retention and CMOS I/O for low static power. The GM883B suffix designates a ceramic pin grid array package and MIL-STD-883 Class B processing for military and aerospace programs. The dedicated clock pin feeds a global clock network that drives every macrocell register with low skew. Typical applications include military and aerospace avionics, industrial control glue logic, bus interface adapters, state-machine controllers, and address decoding for microprocessor systems. Designers select the EPM5128GM883B when a moderate-density, non-volatile, deterministic-timing logic device is required for harsh-environment programs. When designing with this part, budget for a UV eraser window on the top of the package because the device must be exposed to UV-C light for ~20 minutes to erase. Also verify that 55 ns propagation delay meets the system timing budget; if not, consider the -2 speed grade variant with 45 ns delay.
EPM5128JC - 128-Macrocell MAX 5000 CPLD, 35ns, PLCC-68 | Altera
The Altera EPM5128JC is a 128-macrocell, high-density CMOS Erasable Programmable Logic Device (EPLD) from the MAX 5000 family, housed in a 68-pin ceramic J-leaded PLCC package and rated for commercial operating temperature. According to the manufacturer datasheet, the device integrates 128 macrocells, 8 dedicated input pins, and a programmable AND/OR/XOR logic fabric with a typical propagation delay of 35 ns through the logic array, delivering deterministic combinational and registered logic for glue-logic replacement and bus-interface consolidation. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile, instantly-on programmable logic IC that sits hierarchically below FPGAs and above discrete SSI/MSI glue logic in the digital design stack. CPLDs use EPROM or EEPROM (or flash) configuration memory, so they retain their logic on power-up without external boot devices, and they typically provide predictable timing with pin-to-pin delays in the 5-15 ns range, making them ideal for address decoding, bus arbitration, and state-machine implementation. The MAX 5000 series was Altera's second-generation high-density family, predecessor to the MAX 7000/MAX 3000A series. Key features of the EPM5128JC include 100% factory-tested logic, 128 macrocells with programmable I/O architecture, a global clock network, and an in-system-erasable EPROM cell that allows unlimited reconfiguration under UV erasure for ceramic-windowed packages. The device operates from a single 5 V supply, supports both combinatorial and registered logic per macrocell, and provides JTAG-compatible boundary-scan testability per IEEE 1149.1. The architectural foundation is a programmable AND/OR array: each macrocell contains a sum-of-products logic block, a programmable flip-flop, and an output enable / polarity control. The interconnect fabric uses Altera's classic Universal FastTrack (in MAX 5000) routing, which guarantees fixed and predictable timing for every signal path regardless of logic placement, an important consideration when migrating from discrete PAL/GAL devices. Typical applications include legacy 5 V bus-interface bridging (ISA, VME, STD), state-machine controllers in industrial PLCs, peripheral glue-logic consolidation in printers and disk controllers, address decoding for 8-bit and 16-bit microprocessor systems, and pin-compatible replacements for multiple TTL/MSI packages. The ceramic PLCC-68 (JC) package is well-suited for prototypes and high-reliability applications where plastic packages are unsuitable. Designers should note that the MAX 5000 family is an obsolete legacy family; current designs should target MAX 3000A, MAX II, or MAX V CPLDs in equivalent logic densities, or use small low-cost FPGAs (Cyclone IV / MAX 10) when supply assurance matters. The ceramic JLCC windowed package is preferred for engineering development because UV erasure allows iterative reprogramming; production plastic-encapsulated variants should be sourced for volume runs. This page synthesizes distributor availability, drop-in cross-family alternatives, and practical design notes not consolidated in the original Altera datasheet, enabling engineers evaluating legacy MAX 5000 designs to identify drop-in replacements and migration paths.
EPM5128JC-1 - 128-Macrocell MAX 5000 CPLD 40ns | Altera
The Altera EPM5128JC-1 is a high-density UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 macrocells and 2,500 usable gates in a 68-pin ceramic windowed CQCCJ (J-Lead) package. Per the Altera MAX 5000 datasheet, the device operates from a single 5 V supply (4.75 V to 5.25 V) and supports pin-to-pin propagation delays of 40 ns at the commercial speed grade -1, with a maximum toggle frequency of 62.5 MHz. The non-volatile, erasable architecture makes it suitable for prototyping and field-programmable production runs where in-system re-programmability is desired. What is a CPLD? A Complex Programmable Logic Device is a non-volatile programmable logic device that uses a sum-of-products (AND/OR) architecture with on-chip EEPROM or EPROM cells to retain the configuration permanently without external boot memory. CPLDs sit between simple SPLDs/GALs and larger FPGAs in the programmable logic hierarchy, offering deterministic timing, very low power consumption, and instant-on behavior at boot. The MAX 5000 family was Altera's third-generation CPLD, superseded by MAX 7000 and later MAX II families, but remains in use in legacy industrial, telecom, and aerospace systems. Key features of the EPM5128JC-1 include 128 macrocells organized in Logic Array Blocks (LABs), programmable interconnect with predictable timing, a JTAG-compatible programming interface, and 100% AC testability at production. The ceramic windowed J-lead package (CQCCJ-68) allows the EPROM-based configuration to be erased with UV light, supporting iterative prototyping and program updates that flash-based CPLDs cannot match. Architecturally, the device combines multiple PAL-like macrocells with a global programmable interconnect array (PIA), giving designers 5 ns internal register-to-register delay budgets that are independent of routing path length. This deterministic timing model simplifies static timing closure versus FPGA fabrics. Typical applications include legacy industrial glue logic, address decoding and bus interfacing for microprocessors/microcontrollers, state-machine controllers in telecom infrastructure, prototyping of TTL/74-series replacement logic, and aerospace/military systems that require UV-erasable, non-volatile programmable logic with long-term traceability. Today the part is mainly sourced through distributors stocking end-of-life inventory. When designing with this part, prefer the latest revision tool flow (MAX+PLUS II or Quartus II legacy support) and budget for ceramic package clearance. UV erasure requires the quartz window to remain uncovered during reprogramming cycles. This page synthesizes distributor pricing, parametric comparison with same-family MAX devices, and lifecycle guidance not consolidated in the original datasheet.
EPM5128JC-2 - 128-Macrocell UV PLD, 45ns, CQCC-68 | Altera
The Altera EPM5128JC-2 is a high-density, UV-erasable programmable logic device (PLD) from the classic MAX 5000 family, offering 128 macrocells, 7 dedicated inputs, and a maximum propagation delay of 45 ns in a 68-terminal ceramic quad flat pack (CQCC) windowed package. It operates at a maximum clock frequency of 50 MHz and is implemented in CMOS technology optimized for high-speed, high-density glue-logic applications. The J-suffix package with C-windowed top is intended for engineering development and field re-programmability via ultraviolet erasure. A PLD (Programmable Logic Device) is a generic class of digital semiconductor that allows the designer to implement custom combinatorial and sequential logic by programming an on-chip AND/OR array, in this case a sum-of-products macrocell fabric. Within the broader programmable logic hierarchy, the EPM5128 sits at the entry-level/mid-density tier between classic PAL/GAL devices and modern SRAM-based FPGAs, and is part of the one-time-programmable (OTP) or UV-erasable segment that was eventually superseded by EEPROM/Flash-based MAX 7000/MAX 3000 and SRAM-based FLEX/ACEX families. Key features of the EPM5128JC-2 include 128 macrocells of sum-of-products logic, a 45 ns pin-to-pin propagation delay, 50 MHz maximum internal counter frequency, 7 dedicated data inputs, and 7.5 ns input setup time. The device also provides 12 mA DC output drive on each I/O pin, support for both combinatorial and registered macrocell configurations, and an internal global clock network. The J-suffix windowed ceramic package allows up to 1000 erase/program cycles for iterative development and field firmware changes. From an architecture perspective, the EPM5128JC-2 uses a programmable AND array feeding a fixed OR array within each macrocell, with output polarity and feedback paths that are user-configurable. The 50 MHz fCNT figure is derived from the internal counter path rather than the slower tPD path, so designers should follow the 45 ns tPD specification for combinational paths and the 50 MHz figure for registered/counter paths. The 7 dedicated inputs are useful for synchronous control signals such as clock, clock enable, asynchronous clear, and output enable that need to be routed to every macrocell. Typical applications for the EPM5128JC-2 include bus-interface glue logic in 5 V VME and Multibus II systems, state-machine controllers in industrial automation, address decoding for legacy 8-bit and 16-bit microprocessors such as the 8086, 68k, and 68000, peripheral chip-select generation, and DMA/arbitration logic. The wide 5 V tolerance, 128 macrocell density, and 45 ns tPD made it a workhorse for board-level designers in the late 1980s and early 1990s, and windowed ceramic parts remain in service today in long-lifecycle military and aerospace programs where PCB redesign is impractical. A key design consideration is that the J-windowed ceramic package is larger and more expensive than plastic PLCC alternatives, so production builds should migrate to the LC (PLCC-68) or GM (PGA-68) variants once the design is stable. Designers should also budget for the 7 dedicated input pins being non-allocatable as I/O, which reduces effective I/O count compared to the raw macrocell figure. This page synthesizes distributor pricing, package-level drop-in alternatives from the MAX 5000 family, and practical design notes for legacy PLD migration that are not present in the original Altera datasheet.
EPM5128JI - 128-Macrocell MAX 5000 UV PLD | Intel / Altera
The Intel / Altera EPM5128JI is a 128-macrocell high-speed, high-density UV-erasable programmable logic device (PLD) from the classic MAX 5000 family. The part provides 128 macrocells of combinational and registered logic in a 68-terminal ceramic CQCC windowed (J-lead) package and operates with a typical propagation delay of 55 ns and a maximum clock frequency of 40 MHz on a CMOS process. The "J" suffix denotes the ceramic J-leaded CQCC carrier and the "I" indicates the industrial operating temperature grade. A UV-programmable Logic Device (PLD) is an early-generation programmable logic IC that uses floating-gate CMOS memory cells to store the user's logic. UV PLDs like the EPM5128JI are erased by exposing the die through a quartz window to ultraviolet light, then reprogrammed - which is why EPM5128JI is shipped in a ceramic windowed package. UV PLDs sit in the hierarchy: PLD -> programmable logic -> digital logic IC -> semiconductor. They preceded modern SRAM-based CPLDs and FPGAs and are still found in long-lifecycle industrial and military programs. Key features include 128 macrocells, 55 ns pin-to-pin propagation delay (tPD), 40 MHz maximum internal operating frequency, CMOS technology with low standby current, JTAG-less in-system configuration support via the Altera MAX+plus II programming flow, and a 68-terminal ceramic CQCC (J-lead, windowed) package. The windowed ceramic carrier allows repeated erasure and reprogramming, which is why this package form factor remains common in legacy test, military, and avionics designs where code revisions are expected over a 20-30 year program lifetime. The EPM5128JI uses Altera's classic MAX architecture: a global interconnect array feeding an AND/OR logic fabric followed by a configurable output macrocell with a programmable flip-flop. Because the device is pin-compatible with later MAX 5000 speed grades (-2, -1) and compatible with Altera's industry-standard MAX+plus II development flow, it remains a known quantity in maintenance and retrofit programs. Typical applications include industrial control logic, legacy glue logic in military and avionics systems, custom state machines, address decoding, and bus-interface bridging. The wide operating temperature range and ceramic package make the EPM5128JI suitable for harsh-environment programs. When designing with this device, note that 55 ns tPD is too slow for any high-speed synchronous interface - it is best used for control-plane logic, address decoding, and slow asynchronous glue. Programming requires a UV eraser and an Altera-compatible programmer, so for new designs consider the EPM5128JC (plastic PLCC) or a modern MAX II/MAX V CPLD instead. This page synthesizes distributor pricing, drop-in alternatives from the same MAX 5000 family, and practical design notes that are not found in the original manufacturer datasheet.
EPM5128JI-2 - 128-Macrocell UV PLD, 45ns, MAX 5000 | Altera
The Altera EPM5128JI-2 is a UV-erasable programmable logic device (PLD) from the classic MAX 5000 family, providing 128 macrocells, 7 dedicated inputs, 52 user I/O pins, and a 45 ns propagation delay in a ceramic J-leaded (JI) through-hole package. The part operates from a single 4.5 V to 5.5 V supply, supports a maximum clock frequency of 50 MHz, and is characterized across the industrial -40 C to +85 C temperature range, making it suitable for legacy industrial, telecom, and military systems still in long-term production or sustainment programs. A PLD (Programmable Logic Device) is a class of digital integrated circuit whose logic function is defined after manufacturing by the end user. PLDs sit in the broader hierarchy of digital logic devices: PLD -> CPLD (Complex PLD) -> programmable logic -> semiconductor. The MAX 5000 series uses a CMOS EPROM cell with UV-erasable window (JI suffix) and represents Altera's second-generation high-density PLD architecture, predating the modern MAX 7000/3000A families that later moved to in-system programmability (ISP) and lower-cost plastic packages. Key features include 128 macrocells of combinational and registered logic, 52 bidirectional I/O pins organized into architecturally flexible logic array blocks (LABs), and a worst-case pin-to-pin propagation delay (tPD) of 45 ns. The device is built on an EPROM-based CMOS process, is one-time field-programmable through a standard PLD programmer, and is erased by exposure to UV light through the ceramic package window. The JI package is a ceramic J-lead through-hole form factor with an integrated quartz erasure window, optimized for engineering development and long-term aerospace/defense programs requiring field-reprogrammability. From an architectural standpoint, the MAX 5000 family introduced Altera's segmented interconnect and LAB-based macrocell structure that became the blueprint for later MAX 7000 designs. Each macrocell contains a programmable AND/OR array, a flip-flop, and an I/O control block, with product-term allocation across LABs to optimize wide logic functions. The JI-2 speed grade represents the slower (lower-cost) industrial-speed bin, while 'JI' indicates the ceramic J-lead industrial-temperature package - all three designators together define the full ordering part number. Typical applications include legacy glue logic replacement in industrial controllers, telecom interface adapters, prototype and breadboard designs where the UV window enables rapid design iteration, and aerospace/defense sustainment programs where MAX 5000 parts remain on qualified parts lists. The 52 I/O pins are well matched to bus-interface, address-decoding, and state-machine consolidation tasks. When designing with this part, note that EPM5128JI-2 is a mature, NRND/EOL-era device - new designs should consider MAX 7000AE or MAX II/MAX V CPLDs as modern equivalents. Programming requires a legacy PLD programmer (e.g., Altera PL-ASAP or BP-1200) and the MAX+PLUS II software toolchain, both of which are end-of-life. The ceramic JI package is not drop-in compatible with plastic J-lead (JC) or PLCC packages - PCB footprint and pinout orientation differ. This page synthesizes distributor availability, same-family MAX 5000 drop-in alternatives, and design-sustainment notes not consolidated on any single datasheet or distributor listing.
EPM5128LC-1 - 128-Macrocell MAX 5000 CPLD | Altera | 5V 68-Pin PLCC
The Altera EPM5128LC-1 is a 128-macrocell, UV-erasable/OTP CMOS Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, housed in a 68-terminal J-lead ceramic chip carrier (windowed/erasable package) and rated for commercial 5V operation. Built on a 5 µm double-metal EPROM process, the device combines high logic density with predictable, deterministic 30 ns pin-to-pin delay, enabling straightforward replacement of discrete SSI/MSI glue logic. It provides 7 dedicated inputs and 52 bidirectional I/O pins for up to 60 inputs and 52 outputs, with 128 macrocells distributed across the MAX classic Logic Array Block (LAB) fabric. A Complex Programmable Logic Device (CPLD) is a non-volatile, electrically programmable logic IC that integrates multiple PAL/GAL-like macrocell arrays onto a single die with a global interconnect matrix. Within the broader hierarchy, the EPM5128LC-1 sits as: CPLD -> programmable logic device -> logic IC -> semiconductor IC. CPLDs are favored over discrete TTL/CMOS glue logic because they offer deterministic timing, lower board area, lower power, and field re-programmability, while remaining far simpler to use than FPGA & CPLD-class SRAM-based FPGAs. Key features include 128 macrocells, 52 user I/O pins, 7 dedicated input pins, an internal tpd of 30 ns, and an industry-standard 4-pin JTAG (IEEE 1149.1) interface for in-system boundary-scan testing and ISP. The device is offered in the LC package suffix - a windowed ceramic J-lead PLCC that supports UV erasure and re-programming, which makes the LC variant especially valuable for prototyping, design iteration, and low-volume engineering builds. Typical applications include address decoding for 8/16-bit microprocessor and microcontroller systems, bus-interface glue logic between legacy peripherals, board-level control sequencers, and retrocomputing or industrial controller logic. The wide 5V operating range and CMOS input thresholds make the EPM5128LC-1 compatible with TTL and CMOS logic families used in 1980s-1990s designs. When designing with this device, verify JTAG chain order against other boundary-scan devices and note that Altera legacy MAX 5000 software support requires MAX+PLUS II or Quartus in legacy compatibility mode.
EPM5128LC2 - 128-Macrocell MAX 5000 CPLD, 45ns, 5V | Altera
The Altera EPM5128LC2 is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, providing 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It operates from a single 5 V supply and offers a pin-to-pin propagation delay of 45 ns, making it suitable for replacing multiple TTL/74-series glue-logic packages with a single in-system programmable device. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines the integration density of an FPGA with the deterministic timing and instant-on behavior of classic PAL/GAL architectures. Within the broader semiconductor hierarchy, CPLDs sit alongside FPGAs under the programmable-logic umbrella, but unlike SRAM-based FPGAs they retain their configuration in on-chip EPROM/EEPROM cells and require no external boot memory. The MAX 5000 series specifically targets TTL-compatible, 5 V-only glue-logic consolidation and bus-interface replacement in industrial control, telecommunications, and legacy computer designs. Key features of the EPM5128LC2 include 128 macrocells, 8 LABs linked by a global PIA, 1 dedicated global clock input plus shared input/clock pins, JTAG/IEEE 1149.1 boundary-scan support, and an extended operating temperature grade. The device is offered in a Pin-Grid-Array (PGA) ceramic package suitable for socketed or through-hole industrial assemblies, with the 'LC2' suffix indicating the lower-power CMOS process and the commercial speed/power grade. Architecturally, the MAX 5000 device uses an EPROM-based configuration cell so the programmed logic is retained without power, enabling true instant-on behavior at power-up - a defining advantage over SRAM FPGAs in deterministic boot applications. Each macrocell contains a programmable AND/OR array with a flip-flop, and the deterministic PIA routing provides predictable, fixed propagation delays that simplify static timing closure in control and interface designs. Typical applications include TTL/74-series glue-logic consolidation in industrial controllers, address decoding and bus interfacing in legacy x86 and embedded CPU designs, state-machine and sequencer replacement in telecommunications line cards, and I/O expansion for microprocessor-based systems. The 5 V supply, ceramic packaging, and -40 C to +85 C extended commercial operating range also suit it to harsh-environment industrial equipment. When designing with the EPM5128LC2, engineers should note that the MAX 5000 family has been classified as mature/EOL by Altera (now part of Intel), so long-term production planning and last-time-buy windows must be confirmed with the manufacturer before committing to new designs. Use the Altera MAX+PLUS II or Altera Quartus legacy support tools for design entry, fitting, and programming of this older device. This page synthesizes distributor pricing, same-brand drop-in alternatives from the MAX 5000 family, and practical design notes that go beyond what the manufacturer datasheet alone provides.
EPM5130GI - 128-Macrocell MAX 5000 UV PLD | Altera
The Altera EPM5130GI is a UV-erasable, high-density CMOS Programmable Logic Device (PLD) from the classic MAX 5000 family, delivering 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). It supports one global external clock, provides 19 dedicated inputs, 68 total inputs, and 48 bidirectional I/O lines, with a propagation delay (tPD) of 55 ns and a maximum clock frequency of 33.3 MHz, all housed in a ceramic Pin Grid Array (PGA) windowed package suitable for prototype and low-volume engineering work. What is a Programmable Logic Device (PLD)? A PLD is a general-purpose digital integrated circuit whose internal logic function is defined by the end user rather than the device vendor. PLDs sit in the broader taxonomy of logic semiconductors, beneath programmable logic and above fixed-function gate arrays, and historically bridge the gap between discrete 7400-series SSI/MSI TTL packages and modern FPGAs. The MAX 5000 family is a second-generation multi-level AND-OR architecture that consolidated dozens of SSI/MSI functions into one programmable part, an early step toward the high-density CPLDs and FPGAs that dominate today's logic design landscape. Key features of the EPM5130GI include a 100% generic, JTAG-free architecture with 100% interconnect coverage between LABs and macrocells, individual macrocell register control, programmable output polarity, and a 5 V CMOS core compatible with TTL input levels. Programmable output slew-rate control, 100% testable with a high fault coverage, and a ceramic-windowed PGA package suitable for erasure by ultraviolet light round out the silicon feature set. The MAX 5000 architecture separates logic from I/O using a Programmable Interconnect Array (PIA) that is fixed in delay regardless of routing, simplifying timing analysis. Each macrocell contains a programmable AND/OR/Register structure with a D flip-flop and a tri-state output buffer, allowing every output to be configured as combinatorial or registered. The PIA delays are predictable, which historically allowed the MAX 5000 family to replace large amounts of SSI/MSI logic with a single, fully deterministic device. Typical applications for the EPM5130GI include legacy industrial control glue logic, bus-interface address decoding, state-machine implementation, and replacement of large SSI/MSI TTL boards. The 55 ns tPD makes the device suitable for microprocessorial peripheral decoding, peripheral-interface state machines, and older control systems where the surrounding logic is still 5 V TTL. When designing with this part, note that the 'GI' suffix denotes a ceramic PGA windowed (UV-erasable) package intended for prototype and engineering use; production users normally move to the plastic-windowless or one-time-programmable variants after design freeze. Power sequencing should respect standard 5 V CMOS rails, and unused I/O pins must be left floating per MAX 5000 family guidelines. This page synthesizes distributor pricing, drop-in alternatives, and engineering notes not found in the original Altera datasheet alone, so that designers maintaining legacy systems can quickly evaluate the EPM5130GI against modern and same-family substitutes.
EPM5130GM883B - Military CPLD, MAX 5000, 100-pin CPGA | Altera
The Altera EPM5130GM883B is a high-density, high-speed CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, screened to MIL-STD-883B specifications and housed in a 100-terminal Ceramic Pin Grid Array (CPGA) package designated S-CPGA-P100. The /883B suffix indicates Class B MIL-STD-883 screening, which qualifies the device for aerospace, defense, and other high-reliability programs requiring extended temperature operation and traceability. The MAX 5000 architecture combines multiple Logic Array Blocks (LABs) and a programmable interconnect array, providing non-volatile, instant-on logic with deterministic timing suitable for replacing multiple SSI/MSI glue-logic devices. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits between simple PLDs and FPGAs in the programmable logic hierarchy. CPLDs use EEPROM or flash-based configuration cells and a continuous, predictable routing fabric with predictable pin-to-pin delays. Compared to discrete 74-series logic, a CPLD reduces board area, simplifies BOM, and adds design flexibility, while offering faster, more deterministic timing than an FPGA. The EPM5130GM883B is one of the highest-density members of the legacy MAX 5000 family, with up to 5,000 usable gates, making it appropriate for state machines, address decoding, bus arbitration, and peripheral control in legacy military systems. Key features include up to 5,000 usable gates, 128 macrocells, up to 60 user I/O pins, propagation delays on the order of 15 ns, and a 5 V tolerant core designed for TTL-compatible logic levels. The non-volatile EEPROM configuration means the device powers up fully operational without external boot memory, which is critical for safety-critical systems where determinism at power-on is mandatory. Programmable security bits protect the user's design against reverse engineering. The EPM5130GM883B utilizes Altera's MAX architecture with multiple Logic Array Blocks (LABs), each containing 16 macrocells. Each macrocell contains a programmable AND/OR array, a flip-flop, and configurable I/O architecture. The hierarchical interconnect network (PIA) provides predictable routing delays regardless of fan-out, which is a defining advantage over FPGA-based solutions. Typical applications include military avionics, aerospace flight-control subsystems, missile guidance electronics, radar signal processing front-ends, and legacy defense retrofit programs where long-term product lifecycle and MIL-STD-883B traceability are required. The 5 V tolerance and instant-on behavior suit it for retrofits into older 5 V digital designs. A key design consideration when using this part is that the MAX 5000 family is mature/legacy. Engineers should validate long-term availability, second-source the design where possible, and consider newer MAX II/MAX V CPLDs in 3.3 V designs unless MIL-STD-883 screening is mandatory. This page synthesizes distributor pricing, MIL-STD-883B screening details, application context, and design notes that are not aggregated in a single datasheet source. Information reflects the Altera MAX 5000 datasheet family and distributor inventory snapshots as of 2026-09-12.
EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
The Altera (now Intel) EPM5130JC-1 is a high-density UV-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, featuring 2,500 usable gates organized as 128 macrocells in 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), housed in an 84-pin PLCC package. The device operates from a single 5 V supply with 128 macrocells, supports a maximum clock frequency of 62.5 MHz, and delivers a pin-to-pin propagation delay of 40 ns at commercial-grade timing. A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-backed programmable logic IC that combines the integration density of an FPGA with the deterministic timing, instant-on behavior, and simple programming model of a classic PLD. Within the broader programmable-logic taxonomy, the MAX 5000 sits between classic 7400-series SSI/MSI glue logic and modern SRAM-based FPGAs; it functions as a glue-logic replacement, bus-interface bridge, or state-machine engine in industrial, telecom, and military systems where deterministic 5 ns-class pin-to-pin delays and zero-config startup are mandatory. Key features include 19 dedicated inputs, a shared input/clock architecture, 80 I/O pins in the 84-pin PLCC package, and one global clock pin with user-configurable polarity. The architecture uses 100% CMOS EEPROM cells (for MAX 5000AE variants) or EPROM (for the EPM5130 JC-1, which is UV-erasable through a quartz window). Logic is implemented using sum-of-products expressions evaluated by the AND-OR array, with each macrocell containing a programmable flip-flop, select-mux, and feedback path. Typical applications include industrial-control state machines, bus-interface glue logic (8086/68000 glue), address decoding, DRAM controller glue, and legacy 7400-series logic consolidation. The device's 5 V tolerance and deterministic timing also make it suitable for replacing multiple discrete TTL/CMOS packages in designs where PCB real estate is at a premium. This page synthesizes distributor stock, drop-in same-package alternatives from the MAX 5000 family, and design notes that complement the manufacturer datasheet.
EPM5130JI - 128-Macrocell MAX 5000 EPLD, 33.3 MHz | Altera
The Altera EPM5130JI is a CMOS UV-erasable programmable logic device (EPLD) from the MAX 5000 family, featuring 128 macrocells organized into 8 Logic Array Blocks (LABs) interconnected through a Programmable Interconnect Array (PIA), and housed in a ceramic-windowed J-lead package for in-system erasure with ultraviolet light. An EPLD (Erasable Programmable Logic Device) is a non-volatile, reprogrammable digital logic IC that predates modern flash-based CPLDs and FPGAs. The MAX 5000 family sits in the historical Altera (now Intel) product lineage as a high-density, high-speed CMOS EPLD family built around a sum-of-products macrocell architecture with a unified interconnect matrix. This places the EPM5130JI in the hierarchy: macrocell -> LAB -> EPLD -> programmable logic device -> digital IC -> semiconductor. Key features include a maximum clock frequency of 33.3 MHz, a propagation delay of 55 ns (tPD), 1 dedicated external clock input with shared input/clock pin capability, and a 100% factory-tested logic macrocell count of 128. The device is built on a 0.75-micron CMOS EPROM process and is packaged in a ceramic J-leaded chip carrier (JLCC) with a quartz erasure window - a hallmark of the MAX 5000 family. The EPM5130 architecture uses a Programmable Interconnect Array to route signals between LABs, providing fast, predictable timing for state-machine and glue-logic designs. The 128 macrocells each contain a programmable AND/OR array and a configurable flip-flop, supporting registered, combinatorial, and buried logic. Power consumption is roughly 250 mW at typical CMOS supply levels, and inputs are TTL-compatible. Typical applications include legacy telecom interface glue logic, industrial control state machines, prototyping platforms for ASIC replacement, and educational laboratory courses on programmable logic. The UV window allows engineers to erase and re-program the device dozens of times, making it attractive for design iteration. When designing with the EPM5130JI, note that the ceramic JLCC package requires a through-hole socket or careful hand-soldering and that UV erasure takes 20-30 minutes of exposure to 12,000 uW/cm² UV light. The device operates from a single 5V supply and is a commercial-temperature-grade part. This page synthesizes legacy distributor stock data, J-lead package information, and cross-family replacement guidance not consolidated in the original Altera datasheet, helping engineers evaluate the part for both new designs and legacy repair scenarios.
EPM5130LC - 128-Macrocell MAX 5000 UV-Erasable CPLD | Altera
The Altera EPM5130LC is a 128-macrocell, UV-erasable/OTP Complex Programmable Logic Device (CPLD) from Altera's MAX 5000 family, fabricated in CMOS technology and housed in a J-Lead Ceramic Chip Carrier (JLCC) package. It delivers a pin-to-pin propagation delay of 55 ns, supports a maximum internal clock frequency of 50 MHz, and provides 8 Logic Array Blocks interconnected by a Programmable Interconnect Array (PIA). The device integrates 19 dedicated inputs and 48 bidirectional I/O lines, totaling 68 inputs, and is supplied across a 4.5 V to 5.5 V VCC range with TTL-compatible I/O. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that uses EPROM, EEPROM, or flash memory cells to store configuration. The MAX 5000 family predates the MAX 7000/3000 series and belongs to Altera's classic UV-erasable/OTP taxonomy, sitting at the base of the programmable logic hierarchy: CPLD -> PLD (Programmable Logic Device) -> programmable logic IC -> semiconductor. These parts retain their configuration when powered off and are widely used in glue-logic and bus-interface designs. Key features include 128 macrocells, 48 user I/O, 8 LABs, 1 global clock input, 68 total inputs (dedicated + I/O), and a 55 ns tPD. The chip is built on a 0.7 um CMOS EPROM process and supports in-system programming via Altera's A+PLUS or MAX+PLUS II toolchains. Typical applications include bus-interface and address decoding for legacy microprocessors, glue-logic replacement for 74LS/74F TTL gates, asynchronous state-machine controllers, and industrial control boards where UV-erasable parts are preferred for security reasons. Compared to SRAM-based FPGAs, the EPM5130LC is non-volatile and boots in microseconds. When designing with this device, ensure the VCC rail stays within 4.5 V to 5.5 V and account for the 55 ns propagation delay in worst-case timing analysis. Provide proper decoupling on VCC/GND pairs and respect the 48-I/O and 68-input budgets when allocating pins. This page synthesizes distributor pricing, drop-in MAX-family alternatives, and practical design notes not found in the original Altera datasheet, providing engineering value beyond raw parameter repetition.
EPM5130QC-1 - MAX 5000 5130 Logic Cells UV-Erasable PLD | Altera
The Altera (Intel) EPM5130QC-1 is a UV-Erasable / OTP Complex Programmable Logic Device (CPLD) from the legacy MAX 5000 family, supplied in a 100-pin PQFP package with a 0.635 mm terminal pitch. Built on a CMOS process, the device integrates 5130 equivalent logic cells (macrocell class) intended for high-density glue-logic and state-machine replacement in digital systems. The "-1" speed grade and "QC" package code indicate a commercial-temperature grade PLD housed in a windowed ceramic PQFP suitable for prototype development and UV erasure reprogramming. A Complex Programmable Logic Device (CPLD) is a non-volatile, instant-on semiconductor that combines multiple PAL/GAL-style AND/OR arrays on a single die with on-chip programmable interconnect, EEPROM or EPROM storage, and a fixed number of macrocells. In the broader taxonomy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers predictable timing, deterministic propagation delay, and pin-locking capability while providing significantly higher logic density than discrete 22V10/26V12-era PLDs. CPLDs are typically used as address decoders, bus interface bridges, peripheral glue, and state machines that need to boot in microseconds without external configuration memory. Key feature highlights of the EPM5130QC-1 include its 5130 usable gates (marketing name), 128 macrocells, EPROM-based UV-erasable non-volatile configuration, and a -1 speed grade aimed at general-purpose commercial logic integration. The device operates from a single 5 V supply, supports JTAG-style boundary-scan testing (per MAX 5000 family features), and offers output macrocells with programmable polarity, register/ combinatorial modes, and tri-state control. Compared with later MAX 7000/MAX II families, the MAX 5000 retains the older EPROM cell, requiring a quartz window package for erasure. Architecturally, the MAX 5000 family uses an EPROM-based AND array feeding a fixed OR array per macrocell, with each macrocell containing a flip-flop, output enable, and programmable polarity bit. Programming is performed via industry-standard device programmers and a JTAG/byte-blaster-like interface; erasure of windowed parts (QC package, ceramic) requires 20-30 minutes of 254 nm UV exposure. The 100-pin PQFP provides ample I/O for bus-oriented glue-logic tasks, and the 0.635 mm pitch is compatible with conventional surface-mount assembly and hand-soldered rework. Typical applications for the EPM5130QC-1 include industrial control boards, telecommunications equipment glue logic, address decoding for microprocessor/microcontroller systems, peripheral bus bridges (ISA-to-local bus, parallel-port expansion), and educational/prototype lab platforms that require an erasable, reprogrammable logic device. New designs are usually served by MAX II or MAX V devices, but the EPM5130QC-1 remains in service as a form-fit-function replacement for legacy boards where re-layout is impractical. When designing with the EPM5130QC-1, observe the I/O and supply sequencing rules documented in the MAX 5000 datasheet, and ensure all unused I/O pins are configured as outputs with the output-enable disabled or tied to defined logic levels. Because the part is UV-erasable only, a socket is recommended during firmware bring-up. For high-volume production where UV erasure is undesirable, consider migrating to a one-time-programmable (OTP) MAX 5000 variant or to a MAX 7000S / MAX II successor. This page synthesizes distributor pricing, drop-in same-package alternatives sourced from the Altera MAX 5000 family, datasheet availability, and design considerations that are not compiled in the original manufacturer datasheet PDF.
EPM5130WC-1 - 128-Macrocell 40ns UV CPLD, 100-pin CQFP | Intel (Altera) MAX 5000
The Intel (Altera) EPM5130WC-1 is a 128-macrocell ultraviolet-erasable CMOS Complex Programmable Logic Device (CPLD) from the MAX 5000 family, housed in a 100-pin ceramic windowed QFP (Ceramic Quad Flat Pack) package. It delivers a pin-to-pin propagation delay of 40 ns, a maximum clock frequency of 50 MHz, and a logic density suitable for glue-logic, state-machine, and bus-interface consolidation. The ceramic windowed package allows the device to be erased with UV light and reprogrammed, making it appropriate for prototyping and engineering development. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a central interconnect matrix. CPLDs sit in the programmable logic hierarchy above simple PLDs and below FPGAs; they offer predictable timing, deterministic pin-to-pin delays, and instant-on configuration from on-chip EEPROM/EPROM, which makes them especially valuable in address decoding, peripheral control, and bus-interface bridging where sub-nanosecond timing guarantees are required. The EPM5130WC-1 supports up to 100 user I/O through the QFP package, integrates 128 macrocells across multiple Logic Array Blocks (LABs), and provides a programmable interconnect array that maintains consistent timing regardless of how a design is placed. Its UV-erasable windowed package allows iterative reprogramming during development cycles. The MAX 5000 architecture is fabricated on a CMOS EPROM process, providing non-volatile configuration storage. Architecturally, the MAX 5000 family uses a programmable AND/OR array feeding a configurable macrocell register that can be configured as combinational or registered output. Each macrocell includes a flip-flop with programmable clock, clear, and preset controls. The deterministic interconnect fabric guarantees a fixed propagation delay independent of routing density, simplifying static timing analysis. Typical applications include bus-interface glue logic, peripheral address decoding, state-machine controllers, and legacy industrial control systems that require UV-reprogrammable non-volatile logic. The ceramic QFP package is also suited to military and aerospace-grade designs with MIL-STD-883B screening variants available in the MAX 5000 family. When designing with the EPM5130WC-1, account for its 40 ns propagation delay when targeting high-speed bus interfaces and provide proper decoupling on all VCC pins. UV windowed ceramic packages require a label covering the quartz window after programming to prevent accidental erasure from ambient light exposure. This page synthesizes distributor pricing, drop-in same-family alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers source and qualify obsolete Altera MAX 5000 CPLDs.
EPM5130WC-1AA - 128-Macrocell MAX 5000 PLD, 40ns, 50MHz | Altera
The Altera (Intel) EPM5130WC-1AA is a 128-macrocell UV-erasable programmable logic device (PLD) from the MAX 5000 family, offered in a Windowed Ceramic WQFP package with industrial-grade specifications. It features a propagation delay of 40 ns and a maximum clock frequency of 50 MHz, making it a legacy high-density general-purpose PLD for glue-logic and state-machine applications. A UV PLD (Ultra-Violet Erasable Programmable Logic Device) is a non-volatile, one-time or windowed-erasable CMOS logic device that lets designers implement custom combinatorial and registered logic. UV PLDs sit at the bottom of the programmable logic hierarchy, below EEPROM-based CPLDs and SRAM-based FPGAs, and were historically used as flexible pin-compatible replacements for 74-series TTL glue logic. The MAX 5000 family pioneered high-density, high-pin-count UV PLDs by integrating multiple PAL-like Logic Array Blocks (LABs) with a global interconnect, delivering the highest logic-to-pin ratio of any general-purpose PLD of its generation. Key features of the EPM5130WC-1AA include 128 macrocells with 48 dedicated I/O lines plus 19 dedicated inputs (68 total inputs and 48 outputs), 5 V CMOS technology, a maximum propagation delay (tPD) of 40 ns, and a maximum toggle frequency (fCNT) of 50 MHz. Programmable I/O architecture, sum-of-products logic synthesis, and JTAG-free boundary-scan testability were ahead-of-their-time features for early-1990s designs. The windowed ceramic package allows the device to be erased with UV light and reprogrammed many times, supporting iterative development. Architecturally, the EPM5130WC-1AA uses Altera's classic MAX (Multiple Array matriX) architecture: macrocells grouped into Logic Array Blocks share a programmable interconnect array (PIA), with each macrocell containing a programmable-AND/fixed-OR array, a flip-flop, and an output enable. The 5 V CMOS process ensures TTL-compatible inputs and high-drive outputs. Typical applications include legacy industrial control boards, military/aerospace systems requiring windowed-erasable PLDs, telecom interface logic, address decoding, and state-machine replacement of discrete 74LS/74F glue logic. The 50 MHz toggle rate allows it to service medium-speed bus interfaces and decoder pipelines. A key design consideration is end-of-life status: the MAX 5000 family has been NRND/obsolete for over a decade. New designs should use modern MAX II/MAX V CPLDs (e.g., EPM240, EPM570) as drop-in replacements in many cases, although pin-by-pin compatibility is rarely guaranteed. Engineers maintaining legacy systems should plan obsolescence mitigation. This page synthesizes distributor stock indicators, parametric comparison against same-family EPM5xxx variants, and practical design notes for legacy MAX 5000 systems not found in the original datasheet alone.
EPM5130WC-2 - 128-Macrocell UV PLD MAX 5000 | Altera CQFP-100
The Altera EPM5130WC-2 is a high-density, UV-erasable programmable logic device (PLD) from Altera's MAX 5000 family, delivering 128 macrocells with 45 ns propagation delay in a 100-terminal ceramic CQFP (R-CQFP-G100) windowed package. It is built on a CMOS technology node, supports 19 dedicated inputs and 48 bidirectional I/O lines (totaling 68 inputs and 48 outputs), and operates from a single 5V supply (4.75 V to 5.25 V) at commercial 0°C to 70°C temperature range. The windowed ceramic package allows UV erasure and reprogramming of the on-chip EEPROM configuration cells, making this part suitable for prototype development and design iteration cycles where in-circuit reprogrammability is required. A Programmable Logic Device (PLD) is a digital integrated circuit whose logic function is defined by the user after manufacture, rather than being hard-wired at the fab. UV-erasable PLDs such as the MAX 5000 family sit within the broader taxonomy of programmable logic devices (PLDs -> CPLD/PLD -> programmable logic -> digital logic IC -> semiconductor). They are commonly positioned between discrete TTL/CMOS glue logic and FPGAs, offering deterministic timing, non-volatile configuration, and predictable pin-to-pin delays with far lower complexity than modern FPGAs. Key features of the EPM5130WC-2 include 128 macrocells, 45 ns worst-case pin-to-pin propagation delay (tPD), a 0.650 mm terminal pitch gull-wing CQFP-100 ceramic windowed package, single 5V supply operation, and 48 user I/O lines plus 19 dedicated inputs. The MAX 5000 architecture uses EEPROM configuration cells with multi-level AND/OR array logic, providing deterministic combinatorial and registered logic with predictable timing. The device's CMOS technology and MAX 5000 multi-level AND/OR array deliver high density for a 5V PLD with predictable, deterministic timing. Each macrocell includes a programmable register that can be configured as D, T, JK, or SR flip-flop with independent clock and reset, supporting state-machine and registered-logic designs at speeds suitable for control-plane applications. Typical applications include 5V logic replacement in legacy industrial control systems, bus-interface glue logic, address decoding for microprocessor systems, state-machine controllers, and prototype development using UV erasure. Designers favor the MAX 5000 family for its deterministic timing and rugged ceramic packaging. When designing with this device, verify the host PCB's footprint against the 100-terminal CQFP (R-CQFP-G100) land pattern with 0.650 mm pitch. Programming requires a compatible Altera programmer and a MAX+PLUS II or QUARTUS design flow; UV erasure needs a 254 nm UV lamp rated at approximately 25 W·s/cm² integrated dose. Note the part is no longer in active production - plan for last-time-buy or consider MAX 7000/MAX II family successors.
EPM5130WM883B-1 - 128-Macrocell UV PLD, 5V, CQFP-100 | Altera MAX 5000
The Intel (formerly Altera) EPM5130WM883B-1 is a 128-macrocell ultraviolet-erasable programmable logic device (UV PLD) from the MAX 5000 family, supplied in a ceramic-sealed CQFP-100 package and qualified to MIL-STD-883 Class B for high-reliability and military-aerospace applications. It is fabricated in CMOS technology and operates from a single 4.5V to 5.5V supply (nominal 5V), delivering a propagation delay of 55 ns and supporting clock frequencies up to 33.3 MHz. The architecture is built around 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), giving the part a regular, deterministic structure well suited to glue-logic replacement, state-machine implementation and decoder functions in legacy and ruggedised systems. A programmable logic device (PLD) is a non-volatile digital IC whose logic function and interconnect pattern are defined after manufacture by user programming. PLDs sit in the broader hierarchy: PLD -> SPLD/CPLD -> programmable logic -> digital semiconductor. The MAX 5000 series in particular is a Classic SPLD/EPLD line, predecessor to the modern MAX 7000 and MAX II/MAX V CPLD families. Erasable variants such as the EPM5130WM can be erased by exposing the die to UV light through the quartz window of the ceramic package, allowing the same part to be reprogrammed many times - valuable for prototyping and for low-volume production where mask-programmed logic is uneconomic. Key features include 128 macrocells, 19 dedicated inputs and 48 bi-directional I/O pins, one global clock input, and shared input/clock pins with programmable polarity. The I/O structure supports shared inputs and clocks to maximise usable pins and to simplify state-machine and counter designs. With a 55 ns propagation delay the device targets asynchronous logic at moderate frequencies and synchronous logic below 33.3 MHz. The 883B suffix indicates processing in accordance with MIL-STD-883, Test Method Standard for Microcircuits, and the additional '-1' speed/grade suffix denotes a specific propagation-delay bin within the 883B-screened family. The MAX 5000 architecture uses a sum-of-products AND/OR plane plus output macrocells with selectable registered/combinational modes and programmable feedback, allowing implementation of up to 128 product-term logic expressions per device. The 8 LABs feed a central PIA that routes signals between blocks, providing predictable timing that does not depend on placement - a useful property for safety-critical and DO-254 style designs. The device is non-volatile (UV-erasable rather than SRAM-based), so it powers up into the programmed configuration with no external boot memory. Typical applications include military and aerospace avionics, industrial control glue logic, telecom line-card interface logic, instrumentation front-end state machines, and legacy system redesigns where the original PAL/GAL and bipolar PLD must be replaced by a denser, CMOS-equivalent part. The MIL-STD-883B screening also makes it a candidate for ruggedised industrial platforms requiring wider temperature operation and guaranteed baseline reliability. The 'WM' package code denotes a ceramic windowed CQFP-100 suitable for field re-programmability. When designing with the EPM5130WM883B-1, plan power sequencing to avoid latch-up: VCC must ramp monotonically to 5V ±10% before any input or I/O is driven. Inputs are TTL-compatible, but unused inputs should be tied to VCC or GND through a resistor to avoid floating-rail noise. The ceramic windowed package must be shielded from ambient light after programming; opaque labels are recommended. This page synthesises distributor pricing, MIL-STD-883B qualification notes, and pin-compatible drop-in guidance not aggregated on a single manufacturer page.
EPM5130WM883B-2 - 128-Macrocell MAX 5000 UV PLD | Altera | Military
The Altera (now Intel) EPM5130WM883B-2 is a 128-macrocell high-speed, high-density UV-erasable programmable logic device (UV PLD) from the MAX 5000 family, packaged in a military-grade (883B) form factor. It is built on a CMOS process and delivers a worst-case propagation delay of 45 ns (tPD, -2 speed grade), making it suitable for glue-logic and state-machine replacement in legacy industrial and military systems. The device is organized into 8 Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA), with 19 dedicated inputs and 48 user I/O lines for a total of 68 inputs and 48 outputs. A programmable logic device (PLD) is a digital IC whose logic function is defined by the customer after manufacture, typically via non-volatile or UV-erasable fuses/antifuses, sitting in the broader hierarchy of programmable logic -> logic IC -> integrated circuit. MAX 5000 devices are organized as an AND/OR macrocell array optimized for combinational and registered logic, with the -883B suffix indicating MIL-STD-883 Class B processing for extended environmental and reliability qualification. The -2 speed grade designates a 45 ns tPD, the fastest bin of the EPM5130 family (the non-883B EPM5130WM883B runs at 55 ns). Key features include 128 macrocells, 8 LABs, 48 I/O pins, 1 dedicated clock input, and shared inputs/clocks routed through the PIA. The UV-erasable window allows field re-programmability, useful for design iteration on legacy boards. Per the Altera datasheet family document, the EPM5130 is supported by the MAX+PLUS II development environment. Typical applications include military/aerospace digital control, legacy industrial PLC glue logic, address decoding, bus interfacing, and state-machine consolidation in avionics and ground-vehicle platforms. The 883B processing makes the device especially suited for environments requiring controlled components. When designing with this part, verify package pinout against the Altera MAX 5000 datasheet - legacy PLDs often share the same JTAG-style programming interface and require a 12V VPP programming pulse during UV-erase/reset cycles. Pin-compatible MAX 5000 variants (EPM5130WC-1, EPM5130QC-1, EPM5130LC) share logic architecture but differ in package and speed. This page synthesizes distributor pricing, military-grade cross-references, and drop-in MAX 5000 alternatives not consolidated in the original Altera datasheet.
EPM5192-1LC - MAX 5000 CPLD 192-Macrocell 62.5MHz | Altera
The Altera EPM5192-1LC is a 192-macrocell member of the classic MAX 5000 high-speed, high-density programmable logic device family, supplied in a ceramic-windowless ceramic (LC) J-leaded chip-carrier package. It integrates 3,750 usable gates, 192 macrocells and 64 user I/O pins, with a worst-case pin-to-pin propagation delay in the -1 speed grade suited to combinatorial and registered glue-logic tasks at up to 62.5 MHz internal operation. The MAX 5000 architecture combines an EPROM-based AND plane feeding a fixed OR/macrocell array, giving non-volatile, in-system-reprogrammable logic that retains its configuration without battery backup. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that integrates multiple PAL/GAL-style macrocell blocks on a single die. Within the broader taxonomy, CPLDs sit alongside simple PLDs as the "instant-on, deterministic-timing" branch of programmable logic, distinct from SRAM-loaded FPGAs that require a configuration device. MAX 5000 specifically targets high logic-to-pin density in 5 V systems, historically used as bus decoders, address mapping, peripheral glue, and state-machine controllers. Designers choose this family for deterministic propagation delays, zero boot time, and excellent pin-locked retrofits into legacy 5 V backplanes. Key features of the EPM5192-1LC include 192 macrocells across four logic-array blocks (LABs), a programmable interconnect array (PIA), 64 bi-directional I/O pins with individually programmable direction and pull-up resistors, JTAG-compliant IEEE 1149.1 boundary-scan support, and an erasable EPROM process technology that is one-time programmable after window erasure. Power consumption is approximately 0.6 mA standby (outputs disabled) and a few hundred mA dynamic depending on toggle rate and frequency, all on a single 5 V supply. Typical applications for the EPM5192-1LC include 5 V bus arbitration and address decoding in VME/PCI industrial backplanes, peripheral glue logic in legacy telecom and instrumentation chassis, ISA-bus address mapping, custom state machines for motor control, and pin-locked drop-in replacements for vintage 22V10/26V12-style designs requiring higher macrocell count. The 64-pin ceramic J-lead package preserves thermal margin for industrial-grade environments. Designers migrating from 5 V to 3.3 V logic should consider the newer MAX 7000AE or MAX II families; EPM5192-1LC is intended strictly for 5 V legacy systems and is recommended for long-life industrial, military and aerospace retrofits where parts longevity matters more than state-of-the-art density.
EPM51929C - Altera MAX 5000 High-Density EPLD | Intel
The Intel (formerly Altera) EPM51929C is a member of the MAX 5000 family of high-speed, high-density Erasable Programmable Logic Devices (EPLDs) designed for integration of multiple programmable logic functions on a single CMOS device. The MAX 5000 family introduced a multi-array matrix architecture, combining fast 20-pin PAL-style logic blocks with a programmable interconnect network, enabling designers to replace dozens of discrete SSI/MSI logic parts with one device. The part is classified as FPGA/CPLD-class programmable logic and is documented in Altera's MAX 5000 datasheet family. A programmable logic device (PLD/EPLD) is a semiconductor integrated circuit that can be configured by the end-user to implement custom digital logic functions. PLDs occupy the intermediate tier between fixed-function ASICs and discrete logic gates: they offer integration density (replacing many 74LS/74HC parts), short development cycles, and in-system reprogrammability for legacy designs. EPLDs use UV-erasable EPROM cells for non-volatile configuration, retaining their logic when power is removed. Within the broader taxonomy: PLD -> EPLD -> CMOS EPLD -> MAX 5000 family -> Altera programmable logic. The EPM51929C specifically targets glue-logic and bus-interface applications requiring high pin count and moderate logic density. Key characteristics include high-density logic integration, multiple macrocell and expander-product-term structures typical of the MAX 5000 family, and CMOS technology for low static power consumption. The MAX 5000 family was widely deployed in late-1980s and 1990s bus-interface, address-decoding, and state-machine designs. Programmability is achieved via EPROM cells, requiring UV erasure for re-programming. The part is sourced today primarily through the obsolete/legacy distribution channel, making it a target for aftermarket and franchised stocking distributors. Typical applications for the EPM51929C include address decoding and chip-select generation in 80x86 microprocessor systems, DMA and interrupt controller glue logic, peripheral bus arbitration in VME/Multibus designs, state-machine controllers in industrial automation, and legacy system refresh where the original MAX 5000 design must be maintained without PCB redesign. The part's high pin count allows integration of multiple wide decoding functions in one package. When designing with the MAX 5000 family, note that parts are programmed using industry-standard PLD programmers that support the JEDEC fuse-map format. UV erasure takes approximately 20-30 minutes under a 12,000 uW/cm^2 UV lamp at 253.7 nm. Static power consumption is low but I/O drive characteristics must be checked against the specific bus interface (TTL/CMOS) used in the target design.
EPM5192AGC - MAX 5000 EPLD, 192 Macro, 84-Pin PGA | Altera
The Altera EPM5192AGC is a high-speed, high-density CMOS EPLD from the legacy MAX 5000 family, providing 192 macrocells and programmable logic capacity in an 84-pin ceramic PGA package. Marketed as part of the MAX 5000 series "High-Speed, High-Density" line, the device delivers the classic Altera second-generation architecture with pin-compatible speed grades and pin counts spanning the entire EPM5192 family. The "AG" suffix denotes the ceramic PGA package family, while the trailing "C" indicates the commercial speed grade. A UV-erasable / OTP Complex PLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines AND/OR arrays with a fixed OR array and is configured by storing charge on floating-gate transistors. The MAX 5000 family sits within the broader taxonomy of programmable logic: PLD -> EPLD/CPLD -> CMOS EPLD -> MAX series, occupying the same architectural lineage as the classic PAL/GAL devices but with higher usable density and deterministic timing. The MAX 5000 family uses a sum-of-products architecture combined with a flexible macrocell, and is electrically erasable (UV window for UV parts, OTP for windowless parts). Key features include 192 macrocells, 100% factory-tested operation across commercial and industrial temperature ranges, programmable security bit for design protection, and a programmable interconnect fabric supporting high-speed logic. The device is fabricated in CMOS technology, delivering low static power consumption compared to bipolar predecessors such as the classic 22V10 PAL family. Multiple speed grades are offered within the EPM5192 base part number. Typical applications include legacy glue logic replacement, bus interface bridging, address decoding, state-machine implementation, and pin-compatible upgrades for older PAL/PLD designs in industrial control, telecommunications infrastructure, and military/aerospace systems. The EPM5192 family is frequently used in long-lifecycle systems where design stability, established silicon, and toolchain maturity are prioritized over cutting-edge density. When designing with this device, confirm the exact speed grade, package variant (PGA window vs. windowless), and operating-temperature range required by the end system, because the family supports multiple variants such as EPM5192AGC-15 and EPM5192AGC-20 that share the same package and macrocell count but differ in propagation-delay specifications. Designers should also confirm programming hardware and software support (e.g., legacy MAX+PLUS II or Altera/Intel-compatible toolchains), as the device is part of a mature, legacy product family.