EPM5130JC-1 - 2.5K Gate 128-Macrocell CPLD | Altera/Intel MAX 5000
부품 번호: EPM5130JC-1 ✗ 단종| 수량 | 단가 | 합계 |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.2 | $132.00 |
| 100 | $11.8 | $1,180.00 |
| 500 | $10.5 | $5,250.00 |
| 1,000 | $9.25 | $9,250.00 |
EPM5130JC-1 개요
A Complex Programmable Logic Device (CPLD) is a non-volatile, flash- or EPROM-backed programmable logic IC that combines the integration density of an FPGA with the deterministic timing, instant-on behavior, and simple programming model of a classic PLD. Within the broader programmable-logic taxonomy, the MAX 5000 sits between classic 7400-series SSI/MSI glue logic and modern SRAM-based FPGAs; it functions as a glue-logic replacement, bus-interface bridge, or state-machine engine in industrial, telecom, and military systems where deterministic 5 ns-class pin-to-pin delays and zero-config startup are mandatory.
Key features include 19 dedicated inputs, a shared input/clock architecture, 80 I/O pins in the 84-pin PLCC package, and one global clock pin with user-configurable polarity. The architecture uses 100% CMOS EEPROM cells (for MAX 5000AE variants) or EPROM (for the EPM5130 JC-1, which is UV-erasable through a quartz window). Logic is implemented using sum-of-products expressions evaluated by the AND-OR array, with each macrocell containing a programmable flip-flop, select-mux, and feedback path.
Typical applications include industrial-control state machines, bus-interface glue logic (8086/68000 glue), address decoding, DRAM controller glue, and legacy 7400-series logic consolidation. The device's 5 V tolerance and deterministic timing also make it suitable for replacing multiple discrete TTL/CMOS packages in designs where PCB real estate is at a premium. This page synthesizes distributor stock, drop-in same-package alternatives from the MAX 5000 family, and design notes that complement the manufacturer datasheet.
드롭인 대체품: EPM5130JC-1 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.
이 시리즈의 변형
다음과 드롭인 호환되는 동일 시리즈 모델: EPM5130JC-1 (동일 폼 팩터 및 풋프린트) — 차이점: Propagation Delay (tPD), Configuration Memory, Device Type, Operating Temperature, Package.
빠른 비교 도구 — 나란히 비교할 대체 부품을 선택하십시오:
EPM5128JC-1
✅ 드롭인✓ 재고 있음
$24.95 / 개
데이터시트 보기 →EPM5128JC
✅ 드롭인✓ 재고 있음
$9.75 / 개
데이터시트 보기 →EPM5128JC-2
✅ 드롭인✓ 재고 있음
$21.75 / 개
데이터시트 보기 →EPM5130JC-1 최대 정격 & 전기적 특성
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Usable Gates | 2,500 gates |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 |
| Maximum Operating Frequency | 62.5 MHz |
| Propagation Delay (tPD) | 40 ns |
| Supply Voltage (VCC) | 5 V |
| Dedicated Inputs | 19 |
| I/O Pins | 80 |
| 패키지 | 84-pin PLCC (J-lead) |
| 실장 유형 | Surface Mount |
| Programming Technology | UV-erasable EPROM (quartz window) |
| Process Technology | CMOS |
| 동작 온도 | 0C to +70C (commercial) |
| External Clock Pins | 1 global clock |
EPM5130JC-1 핀 구성
| 핀 1 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 2 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 3 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 4 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 5 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 6 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 7 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 8 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 9 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 10 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 11 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 12 | I/O — Bidirectional I/O pin (bank 1) |
| 핀 13 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 14 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 15 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 16 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 17 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 18 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 19 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 20 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 21 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 22 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 23 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 24 | I/O — Bidirectional I/O pin (bank 2) |
| 핀 25 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 26 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 27 | GND — Ground |
| 핀 28 | VCC — +5 V supply |
| 핀 29 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 30 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 31 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 32 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 33 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 34 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 35 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 36 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 37 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 38 | I/O — Bidirectional I/O pin (bank 3) |
| 핀 39 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 40 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 41 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 42 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 43 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 44 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 45 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 46 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 47 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 48 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 49 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 50 | I/O — Bidirectional I/O pin (bank 4) |
| 핀 51 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 52 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 53 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 54 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 55 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 56 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 57 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 58 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 59 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 60 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 61 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 62 | I/O — Bidirectional I/O pin (bank 5) |
| 핀 63 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 64 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 65 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 66 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 67 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 68 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 69 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 70 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 71 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 72 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 73 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 74 | I/O — Bidirectional I/O pin (bank 6) |
| 핀 75 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 76 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 77 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 78 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 79 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 80 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 81 | GCLK — Global clock input (dedicated) |
| 핀 82 | OE — Global output enable (dedicated) |
| 핀 83 | I/O — Bidirectional I/O pin (bank 7) |
| 핀 84 | I/O — Bidirectional I/O pin (bank 7) |
일반적인 애플리케이션
EPM5130JC-1 적합 용도: 6 애플리케이션s: Industrial Control State Machines, Microprocessor Bus Glue Logic, Legacy 7400-Series Logic Consolidation, Address Decoding & Chip-Select Generation, DRAM Controller Glue Logic, Telecom Backplane Glue Logic.
Industrial Control State Machines
The EPM5130JC-1's 128 macrocells and deterministic 40 ns pin-to-pin propagation delay make it well suited to implementing multi-state control logic in industrial PLC backplanes, motor-control boards, and conveyor sequencers. The MAX 5000 family instant-on behavior (no configuration PROM needed) guarantees that control logic is live within microseconds of 5 V power-up, critical for safety interlocks that must assert before any host processor boots. Engineers typically synthesize 4-8 FSMs and several decoder blocks per device, replacing 8-14 discrete 74LS/74HC packages and shrinking PCB area by 60-70%.
추천
Microprocessor Bus Glue Logic
The EPM5130JC-1 was extensively used as 8086, 68000, and Z80 bus-interface glue: address decoding, wait-state generation, chip-select steering, and interrupt prioritization. With 19 dedicated inputs and 80 I/O pins, a single device absorbs the decode logic that previously required 3-5 PALs and 74LS138/139 demultiplexers. The 5 V VCC and 5 V-tolerant inputs match legacy microprocessor buses directly, and the 40 ns tPD easily fits within typical 8 MHz 8086 and 12.5 MHz 68000 cycle times.
추천
Legacy 7400-Series Logic Consolidation
When modernizing a 1980s-era PCB stuffed with 74LS/74HC gates, designers drop in an EPM5130JC-1 to absorb 30-50 SSI/MSI functions onto a single 84-pin PLCC. The MAX 5000's sum-of-products AND-OR array directly emulates 74LS151 muxes, 74LS153 selectors, 74LS283 adders, and 74LS374 registers. Power consumption falls to ~50 mA typical versus 1-2 A for the discrete gate equivalent, improving MTBF in legacy industrial and medical equipment still in field service.
추천
Address Decoding & Chip-Select Generation
The EPM5130JC-1's 128 macrocells easily generate 16-32 chip-select lines for memory banks, peripheral chips, and I/O decoders. The 19 dedicated inputs accept full 20-24 bit address buses directly, and the PIA routes the decoded outputs to any of the 80 I/O pins with no skew. Common patterns include decoding 1 MB memory maps into 8-16 chip-selects at 25 MHz, replacing 2-3 PALs and a 74LS138 tree. The non-volatile EPROM programming ensures chip-select polarities survive power cycles without reconfiguration.
추천
DRAM Controller Glue Logic
In 1980s/1990s DRAM memory boards, the EPM5130JC-1 absorbed the address multiplexing (74LS157), row/column strobe generation, and RAS/CAS timing logic that surrounded 41256, 4464, and 1 Mx1 DRAM arrays. The 62.5 MHz internal clock rate covers 100-150 ns DRAM access designs, and the 40 ns tPD allows insertion of one PLD stage between address buffers and DRAM without violating timing margins. Engineers designing memory-expansion cards for VMEbus, Multibus, and STD-bus platforms standardized on MAX 5000 for these reasons.
추천
Telecom Backplane Glue Logic
The EPM5130JC-1 was a workhorse in telecom backplanes for early SS7, ISDN, and T1/E1 line cards, where it handled framing, alarm-generation, and time-slot assignment logic. The 5 V supply matched telecom -48 V brick-fed 5 V rails directly, and the 80 I/O pins easily accommodated 8-bit parallel time-slot buses plus serial framers. The deterministic 40 ns delay was critical for meeting pulse-mask compliance on T1/E1 outputs - jitter from SRAM-based FPGAs would have violated ANSI T1.403 and ITU G.703 templates.
추천
추천 제품 요약
엔지니어링 참조 데이터: EPM5130JC-1 — 비교, 설계 지침 및 규정 준수 정보.
선택 가이드
대체품과의 비교
| 파라미터 | 이 제품 | EPM5128JC-1 | EPM5128JC | EPM5128JC-2 | EPM5130GM883B |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 84-pin PLCC | 84-pin PLCC | 84-pin PLCC | 84-pin PLCC | 84-pin PGA (ceramic) |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| Usable Gates | 2,500 | 2,500 | 2,500 | 2,500 | 2,500 |
| Propagation Delay (tPD) | 40 ns | 45 ns | 50 ns | 60 ns | 40 ns |
| Max Clock Frequency | 62.5 MHz | 55 MHz | 50 MHz | 40 MHz | 62.5 MHz |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -55C to +125C (military) |
| Programming Technology | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM | UV-EPROM (windowed) |
주요 차별점
- Faster speed grade than the MAX 5128 family (vs EPM5128JC-1)
- Highest-density MAX 5000 PLCC variant (vs EPM5128JC-1)
- Commercial-grade temperature range only (vs EPM5130GM883B)
설계 노트
The EPM5130JC-1 is a UV-erasable EPROM device, not EEPROM or flash. To reprogram, you must remove the part from the board and expose it to UV-C light through the quartz window for 20-30 minutes - this is impractical for in-system updates. If your application requires in-system reprogrammability, migrate to MAX 7000 (EEPROM) or MAX II/MAX V (flash) CPLDs that share the Quartus toolchain.
The 84-pin PLCC package has J-leads on 1.27 mm (50 mil) pitch. Recommended land pattern is the standard PLCC-84 socket footprint with a through-hole or SMT retention clip. For prototype work, use a low-profile PLCC socket so failed parts can be swapped without desoldering. Decoupling: place one 0.1 uF ceramic + one 10 uF tantalum within 5 mm of pin 28 (VCC); pin 27 (GND) should connect to a solid ground plane.
The MAX 5000 PIA (Programmable Interconnect Array) routes signals through a single global interconnect matrix, so high-fanout nets can introduce 5-15 ns of additional delay not captured in the 40 ns tPD specification. For designs approaching 25 MHz, run MAX+PLUS II timing analysis with the actual fanout load, and add output registers on high-fanout nets to keep combinational paths short. Use the dedicated GCLK (pin 81) for any net-clock signals above 33 MHz to avoid PIA jitter.
Estimated: at 5 V VCC with 80 outputs switching simultaneously at 1 MHz into 50 pF loads, dynamic power dissipation is approximately (5 V)^2 x 80 x 1 MHz x 50 pF x 0.5 = 50 mW. Static power is ~25 mA x 5 V = 125 mW, dominating total power. The 84-pin PLCC has typical theta_JA of 50 C/W, so junction rise is ~9C above ambient at full load - well within the 0C to +70C commercial range. Add 200 linear feet per minute of airflow if sealing the board in a 60C+ enclosure.
규정 준수 정보
EPM5130JC-1 was manufactured by Altera in the 1990s before RoHS/REACH compliance tracking was standardized. RoHS and lead-free status are not documented in available datasheets; treat as 'unknown' rather than assuming non-compliance. Not AEC-Q100 qualified (commercial grade only).
