집적 회로

하위 카테고리

📁 ADC/DAC 3,100+ 제품 📁 증폭기 IC 1,900+ 제품 📁 오디오 코덱 18 제품 📁 오디오 IC 2 제품 📁 클록 및 타이밍 670+ 제품 📁 Comparator ICs 1 제품 📁 DSP 1,100+ 제품 📁 데이터 수집 IC 2 제품 📁 디지털 포텐셔미터 4 제품 📁 디스플레이 드라이버 및 컨트롤러 1 제품 📁 FPGA & CPLD 7,300+ 제품 📁 인터페이스 IC 3,400+ 제품 📁 LED 드라이버 1 제품 📁 로직 IC 460+ 제품 📁 메모리 IC 870+ 제품 📁 마이크로컨트롤러 20,000+ 제품 📁 마이크로프로세서 4 제품 📁 모터 드라이버 1 제품 📁 기타 1 제품 📁 Sensor and Detector Interfaces 1 제품 📁 특수 IC 15 제품 📁 비디오 IC 14 제품

제품 (39,000+)

EP610DC-30 - Classic EPLD, 16 Macrocells, 30ns | Altera
EP610DC-30

EP610DC-30 - Classic EPLD, 16 Macrocells, 30ns | Altera

The Altera EP610DC-30 is a Classic EPLD (Erasable Programmable Logic Device) featuring 16 macrocells and 300 usable gates, packaged in a 24-pin ceramic DIP (CERDIP) form factor with a 30 ns propagation delay grade. As a member of the EP610 family, this device implements high-performance CMOS EPROM-based programmable logic with pipelined data rates of up to 100 MHz, targeting legacy glue-logic and state-machine replacement tasks in industrial, telecommunications, and aerospace systems. A Classic EPLD is an early-generation programmable logic device that uses EPROM cells to store the configuration. In the broader taxonomy, the EP610DC-30 sits inside the PLD (Programmable Logic Device) family, which is a subset of programmable logic alongside CPLDs and FPGAs. EPLDs were widely adopted in the late 1980s and 1990s as a means of replacing discrete 74-series TTL/MSI glue logic, integrating state machines, address decoders, bus arbiters, and counter/timer functions into a single non-volatile, one-time-programmable (windowed-erasable UV) IC. The Classic device family preceded the MAX series and offers pin-to-pin compatibility across the EP610 and EP910 lines. Key features include 16 macrocells organized in 4 Logic Expanders, 16 dedicated input pins, and 16 I/O pins with output enable control, plus a programmable clock with global and per-macrocell options. The EP610DC-30 supports a maximum toggle frequency of 100 MHz in pipelined mode, delivers a tPD (pin-to-pin propagation delay) of 30 ns in commercial temperature grade, and offers both registered and combinatorial output modes. The device also features a synchronous preset and asynchronous clear network, plus a security bit to protect proprietary designs after programming. Architecturally, the EP610DC-30 uses a sum-of-products (AND-OR-XOR) PLA-like structure with a global interconnect that routes the 16 inputs and 16 feedback paths into 4 Logic Expanders, each producing 4 product terms per macrocell. The JEDEC-standard 24-pin ceramic DIP package supports through-hole mounting, which is typical for legacy and aerospace applications where socketed, field-replaceable logic remains preferred. Typical applications include TTL/MSI glue-logic replacement in industrial controllers, address decoding in 8-bit and 16-bit microprocessor systems (such as 8086 and 68000 bus interfaces), state-machine implementations in telecom and instrumentation, and aerospace/avionics systems requiring ceramic-package reliability. Designers transitioning from 74LS/74ALS logic to a programmable equivalent often select this part for its predictable timing and EPROM non-volatility. When designing with the EP610DC-30, note that ceramic DIP packages require through-hole PCB footprints and are not compatible with modern surface-mount assembly processes. Programming requires a UV-erasable window (no in-system programmability), and design entry uses legacy tools such as Altera MAX+PLUS II or the older A+PLUS environment. Designers should verify second-source availability (Rochester Electronics and Intel/Altera continue to manufacture this part) before committing to new designs.

견적 요청 문의하기
EP610DC-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DC-35

EP610DC-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DC-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 24-pin windowed CERDIP (CDIP-24) through-hole package. It belongs to the Altera Classic device family and is rated for a 35ns pin-to-pin propagation delay (the "-35" speed grade), with pipelined data rates reaching up to 100 MHz. The device provides 300 usable gates, 16 macrocells, and operates from a single 5V supply. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays with a programmable interconnect. CPLDs sit in the broader hierarchy of programmable logic: programmable logic device (PLD) -> CPLD -> programmable logic -> semiconductor. They are commonly used as "glue logic" to replace discrete 74-series TTL gates, state machines, address decoding, and bus interfacing in designs where an FPGA would be over-specified. The EP610DC-35 features a UV-erasable quartz windowed CERDIP package, allowing the device to be erased with ultraviolet light and re-programmed many times - ideal for prototyping and design iteration. The CMOS Classic architecture provides bipolar-compatible speed at CMOS power levels, with deterministic timing that simplifies static timing analysis. Macrocell flip-flops and product-term sharing support both combinatorial and registered logic functions. Typical applications include address decoding and interrupt generation in 8-bit and 16-bit microprocessor systems, bus arbitration and glue logic in industrial controller boards, state-machine-based peripheral controllers, and replacement of multiple discrete PAL/TTL packages. The 5V single-supply operation and 24-pin DIP form factor are convenient for legacy and through-hole designs. When designing with the EP610DC-35, engineers should note that the part is mature/legacy silicon and is supplied today through Rochester Electronics as an authorized Altera/Intel foundry partner. Lead time and pricing should be confirmed at order entry. Use the Altera MAX+plus II or classic Altera programming tools with a compatible parallel-port programmer for device configuration. This page synthesizes distributor pricing, authorized stocking-channel information, drop-in alternatives, and practical design notes for the EP610DC-35 - information not consolidated in the original Altera datasheet alone.

견적 요청 문의하기
EP610DC15 - 16-Macrocell Classic EPLD, 15ns tPD | Intel / Altera
EP610DC15

EP610DC15 - 16-Macrocell Classic EPLD, 15ns tPD | Intel / Altera

The Intel / Altera EP610DC15 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offering a 15 ns propagation delay and pipelined data rates up to 100 MHz in a 24-pin ceramic DIP (CDIP) windowed package. It features PAL-type architecture with 20 inputs, 16 I/O lines, and 160 product terms for flexible combinatorial and registered logic implementation, operating from a single 4.75 V to 5.25 V supply. An EPLD (Erasable Programmable Logic Device) is a type of programmable logic IC that sits in the broader taxonomy of programmable logic devices (PLDs), which also include PALs, GALs, CPLDs, and FPGAs. EPLDs use EPROM or EEPROM cells to store the configuration, allowing them to be re-programmed and reused across design iterations. The Classic EPLD family preceded the modern MAX series and was historically used for glue logic, address decoding, state machines, and bus interfacing before FPGAs became cost-competitive. Key features of the EP610DC15 include 71.4 MHz maximum clock frequency, CMOS technology with low power consumption, in-system erasability via the ceramic-windowed package, and JEDEC-standard pinout for socket compatibility with EP610DC-10/15/20/25/30/35 speed grades. The device supports both combinatorial and registered outputs with user-configurable macrocell flip-flops. The EP610 architecture uses a global bus that distributes product terms to 16 macrocells, each containing a flip-flop and output enable control. This centralized interconnect provides predictable timing with fixed propagation delay, making it well-suited for asynchronous and synchronous logic replacement where deterministic behavior is required. Typical applications include legacy industrial control replacement, address decoding for 8086/68000 microprocessor systems, state machine implementation, bus arbitration logic, and educational lab platforms. The wide supply tolerance and TTL-compatible I/O simplify integration with 5 V logic families. When designing with this device, note that the EP610DC-15 is an NRND/EOL part. New designs should consider the Altera MAX II or MAX V CPLD families, which offer higher density, lower power, and modern packages. The CDIP-24 windowed package requires UV erasure for reprogramming.

견적 요청 문의하기
EP610DC35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DC35

EP610DC35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DC35 (also written EP610DC-35) is a 16-macrocell Classic EPLD from Altera's Classic EPLD family, housed in a 24-pin ceramic DIP (CDIP-24) through-hole package with a 35ns propagation delay grade. It provides 300 usable gates and pipelined data rates of up to 100 MHz, delivering non-volatile, deterministic logic integration for legacy industrial and military designs. Classic EPLDs (Erasable Programmable Logic Devices) are ultraviolet-erasable, CMOS-based programmable logic devices that pre-date modern CPLDs and FPGAs. They belong to the broader category of programmable logic devices (PLDs), which also include SPLDs, CPLDs, and FPGAs. EP610-series devices are organized as a single AND/OR logic block feeding a fixed-output macrocell array, providing predictable timing suitable for address decoding, bus interfacing, and glue-logic replacement in 5V systems. Key features include 16 macrocells, 300 gates of usable logic, a maximum propagation delay of 35ns (tPD), and a 5V single-supply operation with 5V-tolerant I/O. The EP610DC35 is windowed (ceramic DIP with quartz erase window) and is one of the speed grades in the EP610 family, distinguished from -10, -15, -20, -25, and -30 grades by its 35ns timing. The device supports both combinational and registered logic with pin-feedback architecture and is in-system programmable via Altera's classic programming algorithm. Architecturally, the EP610 uses Altera's Classic EPLD macrocell with sum-of-products logic feeding programmable flip-flops, plus a global clock network and JTAG-free programming interface. The 5V CMOS EPROM technology yields high noise immunity and latch-up resistance, making it well suited to industrial control boards, avionics retrofits, and 5V legacy embedded platforms where modern 3.3V/2.5V PLDs are not pin-compatible replacements. Typical applications include 5V bus interface glue logic, address decoding for M68k and x86 embedded systems, state-machine controllers, peripheral chip replacement, and military/aerospace systems requiring 5V tolerance and high reliability. The CDIP-24 ceramic package offers extended temperature performance and is preferred over plastic DIPs in aerospace and defense systems. When designing with the EP610DC35, note that it is programmed with an Altera legacy programmer (e.g., PLDLMax or compatible) and cannot be re-programmed in-system via JTAG. Designs should also budget the 35ns tPD carefully when interfacing to high-speed buses; for faster speeds the EP610DC-25 or EP610DC-20 grades should be considered.

견적 요청 문의하기
EP610DI-25 - 25ns Classic EPLD, 16 Macrocells | Altera (Intel)
EP610DI-25

EP610DI-25 - 25ns Classic EPLD, 16 Macrocells | Altera (Intel)

The Altera (Intel) EP610DI-25 is a 25 ns propagation-delay Classic EPLD (Erasable Programmable Logic Device) featuring 16 macrocells, 16 bidirectional I/O lines, and 4 dedicated inputs, housed in a 24-pin ceramic glass-sealed DIP (R-GDIP-T24) package. The "I" suffix denotes the industrial (ceramic) temperature variant and the "25" indicates the 25 ns tPD speed grade, while the "DI" package code identifies the ceramic DIP through-hole form factor. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device belonging to the programmable logic device (PLD) family, which sits hierarchically between discrete logic gates (lowest density) and modern FPGAs (highest density) in the logic integration taxonomy: discrete logic -> PLD -> CPLD -> FPGA -> SoC FPGA. EPLDs use a sum-of-products (AND-OR) PLA-style architecture with a non-volatile EPROM cell, allowing designers to implement glue logic and state machines that retain configuration after power removal. The EP610 is one of Altera's foundational Classic EPLD parts that helped establish the PLD market. Key features include 25 ns pin-to-pin propagation delay, pipelined data rates up to 100 MHz, 16 macrocells with user-configurable D/T/JK flip-flops, 16 I/O pins, 4 dedicated inputs, and EPROM-based non-volatile configuration. The device offers predictable, deterministic timing identical for every logic path, simplifying static timing analysis compared to SRAM-based FPGAs. A single 5 V power supply and a standard JEDEC programming interface simplify design-in. The EP610DI-25 uses an EPROM-cell CMOS architecture with a programmable AND/OR array. Logic is implemented as sum-of-products expressions with optional registered output via the macrocell flip-flop. This architecture trades flexibility for predictability, making the part well-suited to bus decoding, address decoding, state machines, and custom peripheral interfaces in legacy 5 V systems. Typical applications include TTL/CMOS logic integration, bus decoding and address mapping in 5 V microprocessor systems, peripheral interface glue logic, state-machine controllers, and legacy industrial control replacement. The ceramic DIP package supports through-hole assembly typical of older industrial, military, and aerospace equipment still in service. When designing with this part, note that the device is one-time-programmable only via UV erasure (windowed package), so designers must budget an EPROM eraser step into the prototyping workflow. Programming requires a compatible device programmer supporting the Classic EPLD family. Modern 3.3 V systems require level shifters to interface this 5 V part. This page synthesizes distributor pricing, drop-in replacement MPNs, and design considerations not found in the original 1990s datasheet, enabling accurate sourcing for long-lifecycle equipment support.

견적 요청 문의하기
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30

EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics

The Rochester Electronics EP610DI-30 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 24-pin ceramic DIP (CERDIP-24) windowed package, with a propagation delay of 30 ns and a pipelined data rate of up to 100 MHz. The UV-erasable windowed CERDIP allows the device to be erased with ultraviolet light and reprogrammed in-system, supporting iterative development and field upgrades typical of the original Altera Classic EPLD family. What is a Classic EPLD? An EPLD (Erasable Programmable Logic Device) is a type of programmable logic that sits in the hierarchy between discrete PAL/GAL devices and modern FPGAs/CPLDs. Classic EPLDs use EPROM/EEPROM cells to store AND/OR logic terms and are typically programmed once (one-time-programmable, OTP) or with UV erasure (windowed packages). They fill the role of glue logic, state machines, and address decoding in systems where modern FPGAs would be over-spec and discrete logic would be too bulky. The EP610 belongs to the first wave of commercially successful EPLDs, offering 16 macrocells and reasonable speed at low power for the era. Key features of the EP610DI-30 include 16 macrocells of programmable logic, 30 ns propagation delay (commercial -30 speed grade), a pipelined clock rate of up to 100 MHz, and CMOS technology for low standby power. The device operates from a single 5 V supply and is pin-compatible with the rest of the EP610 family, allowing easy migration across speed grades (tPD = 15, 20, 25, 30 ns) and across package options (DIP, SOIC, ceramic DIP). The architecture is based on a programmable AND/OR array feeding 16 output macrocells with user-configurable registers, I/O direction, and feedback paths. Programming is performed via the standard Altera EP610 programming algorithm through dedicated programming pins on the device. The windowed CERDIP-24 package supports UV erasure for lab development, while the plastic DIP variant is intended for one-time-programmed production. Typical applications include glue logic replacement, address decoding for microprocessor and microcontroller systems, state machines and sequencers, bus interface logic, custom peripheral controllers, and legacy industrial control systems. The EP610 is also widely used in educational settings and as a low-cost entry point for learning programmable logic design. When designing with the EP610DI-30, note that the -30 speed grade is one of the slower variants; for higher throughput consider the EP610DC-15 or EP610DC-20. The CERDIP-24 package consumes substantial board area and the quartz window is sensitive to scratches - cover the window with opaque label after programming to prevent accidental UV erasure. This page synthesizes distributor pricing, package/die equivalents in the EP610 family, and practical design notes not aggregated on the manufacturer datasheet.

견적 요청 문의하기
EP610DI-30N - Classic 16-Macrocell EPLD, 30ns CDIP-24 | Altera
EP610DI-30N

EP610DI-30N - Classic 16-Macrocell EPLD, 30ns CDIP-24 | Altera

The Altera EP610DI-30N is a Classic-family Erasable Programmable Logic Device (EPLD) from the EP610 series, offering 16 macrocells, 300 usable gates, and a 30 ns pin-to-pin propagation delay in a 24-pin ceramic DIP (CDIP) windowed package. Operating from a single 5 V supply, it provides up to 33.3 MHz system clock rates and pipelined data rates reaching 100 MHz, making it well-suited for glue-logic, bus decoding, and state-machine replacement in legacy industrial designs. The 'I' temperature range (-40°C to +85°C) and the 'N' windowed ceramic DIP suffix enable in-system reprogramming via UV erasure, a hallmark of the Classic EPLD family used through the 1990s. An EPLD (Erasable Programmable Logic Device) is a type of non-volatile programmable logic IC that predates modern CPLDs and FPGAs. Positioned in the taxonomy as EPLD -> CPLD -> programmable logic -> logic IC, the EP610 family pioneered the AND/OR fixed-architecture with sum-of-products logic feeding an output macrocell, providing predictable, deterministic timing that rivals discrete TTL glue logic but with much higher integration density. Key features include 16 macrocells, each with programmable I/O polarity, output enable, and feedback, 24 dedicated input pins, a 5 V ±5% supply, and TTL-compatible inputs/outputs. The EP610DI-30N ships as a UV-erasable windowed ceramic DIP, allowing engineers to erase and reprogram the device during development cycles - a significant advantage over one-time-programmable (OTP) plastic-DIP variants. According to the Rochester Electronics datasheet reference, the device is qualified for industrial-temperature operation. The architecture uses a CMOS AND array feeding an OR array into output macrocells, providing predictable tPD timing independent of routing. The 30 ns tPD (suffix -30) places the EP610DI-30N in the mid-speed tier of the Classic EPLD family; faster -25 and -20 grades exist for more demanding glue-logic applications, while slower -35 and -40 grades serve cost-sensitive designs. Typical applications include 5 V bus-interface decoding (e.g., address decoding in 8086/68k/Motorola microprocessor systems), state-machine replacement for discrete 74LS glue logic, custom peripheral controllers in legacy industrial equipment, and prototyping logic for designs that later migrate to a pin-compatible OTP or masked variant. The device is also commonly used to repair or extend legacy boards originally built with the plastic-DIP OTP EP610PC variant. When designing with this device, place 0.1 µF decoupling capacitors within 50 mm of each VCC pin and route ground returns directly to the system ground plane. Note that the windowed ceramic package adds significant vertical clearance (~6 mm) versus plastic DIP - account for this in mechanical enclosures. The EP610DI-30N is widely available through authorized distributors like Rochester Electronics as a long-lifecycle sustainment part for legacy systems. This page consolidates distributor pricing, drop-in same-family alternatives (EP610DI-25, EP610DI-20, EP610PC variants), and practical design notes beyond the bare datasheet, helping engineers source a pin-compatible EPLD for legacy 5 V logic designs.

견적 요청 문의하기
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35

EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera

The Intel / Altera EP610DI-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 family, delivering a propagation delay of 35 ns (tpd) and housed in a 24-pin ceramic DIP (CDIP-24) package. It contains 300 usable gates, 16 macrocells interconnected by a global bus, and 160 product terms, with 16 bidirectional I/O lines and 20 total inputs including 4 dedicated clock/control inputs. The device operates from a single 5 V supply and supports pipelined data rates up to 100 MHz internally, with a maximum external toggle frequency of 28.6 MHz. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable, CMOS-based programmable logic device that predates modern CPLDs and FPGAs, used to implement random-logic glue functions, state machines, and address decoding. EP610 sits in the programmable logic hierarchy: programmable logic device (PLD) > EPLD > Classic EPLD, with macrocell-based architecture serving as a direct replacement for multiple discrete PAL/GAL devices in legacy designs. Key features include CMOS technology for low power consumption, in-system erasability via UV exposure window, registered or combinational macrocell configuration, and synchronous/asynchronous clocking options. The device provides architectural flexibility through output polarity programming and configurable feedback paths on every macrocell. Architecturally, EP610 uses a sum-of-products PLA structure feeding a programmable output macrocell array. Its 16 I/O pins share the global bus, while the 4 dedicated inputs handle clock and control functions. The 35 ns propagation delay positions EP610DI-35 as the mid-speed variant of the family, suitable for applications below 28 MHz toggle rates. Typical applications include legacy industrial control logic, address decoding for 8-bit and 16-bit microprocessor systems, bus interfacing glue logic, state-machine replacement for multiple TTL packages, and educational/prototyping platforms. The CDIP-24 ceramic package also makes it suitable for military and aerospace programs that still require through-hole, ceramic-bodied programmable logic. When designing with EP610DI-35, note that it requires a 5 V supply and UV erasure for reprogramming; a modern Lattice or Xilinx CPLD is a faster, in-system-programmable alternative for new designs. Verify the 24-pin CDIP footprint matches your PCB land pattern before selecting it as a drop-in replacement. This page synthesizes distributor pricing, drop-in Classic EPLD alternatives, and practical design notes not found in the original Altera datasheet.

견적 요청 문의하기
EP610DM-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera
EP610DM-35

EP610DM-35 - 16-Macrocell Classic EPLD, 35ns, CDIP-24 | Altera

The Altera EP610DM-35 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the original Altera Classic family, delivered in a 24-pin ceramic DIP (CDIP) windowed package with a 35 ns propagation delay. It is a UV-erasable, CMOS, PAL-type programmable logic device with 300 gates, 16 macrocells, and a pipelined data-rate capability of up to 100 MHz. A Classic EPLD is a member of the early programmable logic device (PLD) family that preceded modern CPLDs and FPGAs. EPLDs provide sum-of-products logic, macrocell-based I/O, and non-volatile (UV-erasable) configuration in a small pin-count DIP, ideal for glue logic, address decoding, bus interfacing, and state-machine replacement in legacy industrial, telecom, and military systems. The EP610DM-35 sits within the broader taxonomy of programmable logic: PLD -> EPLD -> Classic EPLD -> CMOS PAL-type EPLD. Key features include 24 dedicated input pins, 16 bidirectional I/O macrocells, a 35 ns pin-to-pin propagation delay (tPD), a 100 MHz pipelined fMAX, and a single 5 V supply. The 'D' suffix denotes the ceramic DIP package with a quartz window for UV erasure; the 'M' grade indicates military temperature range (-55C to +125C). The device is reprogrammable, JTAG-free, and uses Altera's MAX+plus II or classic Altera development tools for fitting. Architecturally, the EP610DM-35 uses a programmable AND/OR array feeding 16 output macrocells with user-configurable flip-flops. Each macrocell can be set to combinatorial or registered output with dedicated feedback, allowing state machines, counters, and registered decoders. The Classic architecture is non-volatile, making the part an attractive choice for systems that must boot into a known logic state without external configuration memory. Typical applications include legacy bus-interface glue logic in industrial controllers, address decoding in 80C86/80C88 and Motorola 68000 microprocessor systems, MIL-STD-1553 and ARINC-429 interface adapters, military/aerospace digital subsystems, and replacement of discrete TTL/CMOS glue in long-lifecycle equipment where modernization is impractical. When designing with this device, ensure that the input rise/fall times meet the 5 V CMOS thresholds (typically <100 ns) to avoid spurious transitions, and budget sufficient tCO (clock-to-output) and tSU (setup-time) margins in synchronous paths. The 35 ns grade is appropriate for sub-30 MHz system clocks; for faster designs, select the EP610DI-25 (25 ns) or EP610DM-25 equivalent. This page synthesizes distributor stock data, same-package EPLD alternatives, and design notes not found in the original Altera datasheet, supporting long-tail lifecycle maintenance for this mature Classic EPLD part.

견적 요청 문의하기
EP610DM/883B - 16-Macrocell Classic EPLD, 100MHz, CDIP-24 | Intel
EP610DM/883B

EP610DM/883B - 16-Macrocell Classic EPLD, 100MHz, CDIP-24 | Intel

The Intel (formerly Altera) EP610DM/883B is a high-performance, 16-macrocell Classic Erasable Programmable Logic Device (EPLD) in a 24-pin Ceramic DIP (CDIP) package, qualified to MIL-STD-883 Class B for military and aerospace applications. Pipelined data rates reach up to 100 MHz, with 24 dedicated input pins and 16 output macrocells organized into a programmable AND/OR architecture that replaces multiple SSI/MSI logic packages. A Classic EPLD is an early-generation programmable logic device sitting in the broader taxonomy of programmable logic: PAL -> PLA -> EPLD -> CPLD -> FPGA -> SoC FPGA. Classic EPLDs from the EP610 family use UV-erasable CMOS EPROM cells to store the logic configuration, providing non-volatile behavior without an external configuration memory. The EP610DM/883B is intended for glue-logic, address decoding, state-machine, and bus-interface replacement tasks where pin-count, deterministic timing, and military-grade reliability are required. Key features include 16 macrocells, 24 pins total, dedicated input register paths, and a tPD propagation delay on the order of 25 ns (commercial grade). The /883B suffix indicates full MIL-STD-883 Class B screening, covering extended temperature range, burn-in, and 100% electrical test at temperature corners. The CDIP-24 ceramic package offers hermetic sealing suitable for harsh-environment deployments. The architecture implements a sum-of-products AND/OR array feeding 16 flip-flop-backed output macrocells, with a synchronous clock network and asynchronous clear/preset support on every macrocell. This structure maps cleanly to state machines, decoder logic, and bus-arbitration functions, replacing multiple 74LS/74F TTL packages with one programmable device and reducing board area and BOM count. Typical applications include military and avionics systems, industrial control, legacy replacement of 74-series glue logic, address decoding in VME/VXI backplanes, and radiation-tolerant logic subsystems. The /883B screening makes it suitable for programs requiring MIL-PRF-38535 qualified parts or DESC-approved sources. When designing with this device, note that programming requires a classic EPROM-based programmer (not a JTAG interface). Logic fitting must be verified against the 16-macrocell resource limit; larger designs require migration to MAX series or modern CPLD families. Always derate switching speed at temperature extremes per MIL-STD-883 curves.

견적 요청 문의하기
EP610IDC-10 - 16-Macrocell Classic EPLD, 10ns, CDIP-24 | Altera
EP610IDC-10

EP610IDC-10 - 16-Macrocell Classic EPLD, 10ns, CDIP-24 | Altera

The Altera EP610IDC-10 is a Classic-series Erasable Programmable Logic Device (EPLD) delivering 300 usable gates, 16 macrocells, and a 10 ns pin-to-pin logic delay in a 24-pin ceramic DIP (CDIP) package. It belongs to the original Altera Classic EPLD family, fabricated on advanced CMOS technology, with a 100 MHz maximum counter frequency and 5V TTL-compatible I/O. A Classic EPLD is a non-volatile programmable logic device that combines the density of a small PLD with the speed and pin-count flexibility of early FPGAs. It sits within the broader hierarchy of programmable logic devices (PLD), between simple PAL/GAL arrays and full FPGAs. EPLDs use a sum-of-products architecture with user-programmable AND/OR planes and a fixed, deterministic interconnect, which makes them ideal for fast control logic, address decoding, and state machines where predictable timing is more important than raw gate density. Key features of the EP610IDC-10 include 16 macrocells, 4 dedicated inputs plus 20 I/O pins, an on-chip programmable interconnect, support for 100% TTL emulation, and an integrated test circuitry that allows AC specification verification during production. The device is in-system programmable via the Altera MAX+PLUS II development environment and supports JTAG-style boundary-scan testing on selected package variants. The Classic architecture is macrocell-based: each macrocell contains a programmable flip-flop, configurable I/O, and shared product-term logic that feeds the AND/OR array. Compared with one-time-programmable (OTP) PALs, the EP610IDC-10 is windowed ceramic and therefore erasable with UV light, making it suitable for development and low-volume prototyping rather than high-volume production. Typical applications include high-speed address decoding for 8086/80286-era microprocessor systems, bus interface logic, glue logic in industrial controllers, state machines for instrumentation, and 5V TTL glue-logic replacement. Designers also use Classic EPLDs to consolidate multiple discrete 74LS/74F logic packages into a single programmable device for legacy system refresh. A key design consideration is the 5V supply requirement: the EP610IDC-10 is not 5V-tolerant in a mixed-voltage system, so any 3.3V signals must be level-shifted. The CDIP-24 ceramic windowed package requires a UV eraser socket for reprogramming, so production volumes should migrate to the plastic OTP (one-time-programmable) EP610PC-10 variant. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping engineers evaluate EPLD alternatives for legacy design maintenance and obsolescence avoidance.

견적 요청 문의하기
EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
EP610IDC-15

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

The Intel EP610IDC-15 is a 16-macrocell Classic EPLD from the Altera Classic device family, fabricated in CMOS and housed in a 24-pin ceramic dual in-line package (CerDIP) with a 15 ns propagation delay. It provides 300 usable gates, a 66 MHz maximum operating frequency, and 5V nominal supply operation across the commercial 0C to +70C temperature range. The device implements UV-erasable / OTP logic for in-system prototyping and is supported by the MAX+PLUS II development environment. A Classic EPLD (Erasable Programmable Logic Device) is a member of the SPLD/CPLD hierarchy of programmable logic devices. Architecturally, an EPLD sits between simple PAL/GAL SPLDs and modern high-density CPLDs/FPGAs, offering non-volatile, deterministic combinatorial-and-sequential logic blocks (macrocells) with pin-to-pin timing guarantees. In the broader taxonomy: programmable logic -> SPLD/EPLD -> Classic EPLD -> macrocell array. EPLDs are valued for low-power, deterministic, single-chip glue-logic replacement of discrete 74LS/74HC TTL. Key features of the EP610IDC-15 include 16 macrocells with user-programmable I/O, 24 dedicated input pins, an internal logic-test mode for AC verification during production, pin-to-pin delay of 15 ns, and CMOS standby current well below bipolar predecessors. The CerDIP-24 ceramic package provides hermeticity for legacy industrial and military programs that demand through-hole reliability and DIP-handling compatibility. The architecture is built on a CMOS EPROM cell array driving an AND/OR macrocell fabric with programmable registers. Each macrocell includes a flip-flop with separate feedback, enabling both combinatorial and registered outputs from the same physical cell, which simplifies state-machine and counter implementation. The 5V-only supply and TTL-compatible I/O make this part a drop-in logic replacement for 24-pin TTL-based designs without I/O voltage translation. Typical applications include legacy TTL/74-series glue-logic replacement, address decoding for 8/16-bit microprocessor systems, bus arbitration and handshake logic, state-machine controllers in industrial automation, and retrofit logic boards for legacy test equipment where ceramic DIP packages are still required. Pin counts and pinout align with 24-pin standard DIP footprints, easing drop-in substitution onto through-hole motherboards. When designing with the EP610IDC-15, use a programming current of 11.0 mA typical (per Classic family datasheet), place a 0.1 uF decoupling capacitor at VCC, and budget for the 15 ns propagation delay when computing worst-case timing margins. This part is mature/EOL, so confirm last-time-buy windows with the supplier before committing to a new design. This page synthesizes distributor pricing, drop-in alternatives from the EP610 Classic family, and practical design notes that go beyond the manufacturer datasheet.

견적 요청 문의하기
EP610ILC-10 - Classic EPLD, 16 Macrocells, 10ns tPD, PLCC-28 | Altera
EP610ILC-10

EP610ILC-10 - Classic EPLD, 16 Macrocells, 10ns tPD, PLCC-28 | Altera

The Altera EP610ILC-10 is a 5 V, UV-erasable/OTP Classic-series Erasable Programmable Logic Device (EPLD) housed in a 28-pin plastic J-lead chip carrier (PLCC) package, providing 300 usable gates and 16 macrocells at pin-to-pin logic delays as low as 10 ns and counter frequencies up to 100 MHz. The device implements a PAL-type architecture with 16 dedicated input pins and 16 I/O macrocell outputs, giving designers a glue-logic alternative to small PAL/GAL devices with deterministic, non-volatile 5 V silicon. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that combines the integration density of early PLDs with erasable EPROM-style configuration memory; in the broader taxonomy EPLD -> PLD -> programmable logic -> digital IC, the EP610 sits at the low-density end typically used to replace discrete TTL/CMOS glue logic, state machines, address decoders, and bus-interface functions. The Classic family provides pin-to-pin delays of 10-25 ns and supports counter frequencies up to 100 MHz, making it suitable for synchronous control logic in industrial and embedded systems. Key features of the EP610ILC-10 include 160 product terms, 4 dedicated inputs, 16 I/O pins, and a 5 V single-supply operation; the -10 speed grade delivers 10 ns tPD and 100 MHz fCNT, allowing the device to be clocked at full speed without metastability issues typical of slower PALs. The macrocell architecture supports both registered and combinatorial outputs with feedback, enabling efficient state-machine implementation. The PLCC-28 package uses J-leads suitable for socketed programming and field replacement, which is important for legacy and MIL-spec applications. Typical applications include address decoding in 8086/68000 microprocessor systems, glue logic in VMEbus/ISA backplanes, state machines in industrial controllers, and bus arbitration logic in legacy embedded systems. The 5 V supply and TTL-compatible I/O make the EP610 directly compatible with bipolar and CMOS 5 V logic families including 74LS, 74HC, and 74F series. When designing with the EP610ILC-10, ensure that input rise/fall times remain below the datasheet limit to avoid AC noise issues, and provide proper decoupling with 0.1 uF capacitors on each VCC pin. Because the EP610 is a legacy part with limited current production, engineers should verify lifecycle status with the distributor before committing to new designs and consider pin-compatible successors such as the EP610ILC-12 or EP910 for higher gate counts.

견적 요청 문의하기
EP610ILC-25 - Classic EPLD 300 Gates 16 Macrocells 25ns | Altera
EP610ILC-25

EP610ILC-25 - Classic EPLD 300 Gates 16 Macrocells 25ns | Altera

The Altera EP610ILC-25 is a 25ns Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 series, delivering 300 usable gates, 16 macrocells, and 40 MHz maximum operating frequency in a 28-pin PLCC package. It is a CMOS, PAL-type Electrically Erasable Programmable Logic Device (EEPLD) offering 160 product terms and flexible macrocell output architecture for legacy 5V logic designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines multiple PAL-like macrocell arrays with a central interconnect, allowing engineers to implement custom glue logic, state machines, and bus interface functions without the cost of an ASIC. The EP610 belongs to Altera's Classic EPLD family — the early 5V generation that pre-dated the MAX 7000 series and now sits firmly in the legacy/last-time-buy segment of the Altera (now Intel PSG) catalog. Key features of the EP610ILC-25 include 4 dedicated inputs and 16 bidirectional I/O pins (20 total inputs), 16 macrocells with configurable D/T/JK/SR flip-flop options, 160 product terms for sum-of-products logic, and a 25ns pin-to-pin propagation delay that supports a 40 MHz internal fMAX. The device is electrically erasable, enabling in-system reprogramming during development and field upgrades. It operates from a single 5V supply (4.75V to 5.25V) with commercial temperature range of 0C to +70C. The EP610ILC-25 architecture pairs a programmable AND array feeding a fixed OR array into 16 macrocells, each capable of registered or combinatorial output with selectable feedback paths. The JTAG-less, 5V-only design philosophy makes it a straightforward drop-in for legacy PAL/GAL replacement designs and for engineers migrating older prototype boards into a single, denser, erasable part. Typical applications include legacy glue logic replacement, address decoding for 80C186/80C51 microcontroller systems, bus interface and arbitration logic, 5V state machines in industrial control, and education/lab platforms teaching programmable logic fundamentals. The 28-pin PLCC socket footprint remains widely supported on legacy backplanes and industrial SBCs. When designing with this part, verify that the development toolchain (MAX+PLUS II or older Altera classic support) is still available, as modern Quartus flows may not target the EP610 family. Confirm socket availability — J-lead PLCC-28 sockets are still in production but increasingly specialized. For new designs, evaluate MAX II or MAX V CPLDs as modern equivalents. This page synthesizes distributor stock and lead-time intelligence, pin-compatible same-family drop-in alternatives, and practical legacy-design notes not consolidated in the original Altera datasheet.

견적 요청 문의하기
EP610ILC10 - 16-Macrocell Classic EPLD, 10ns PLCC-28 | Intel
EP610ILC10

EP610ILC10 - 16-Macrocell Classic EPLD, 10ns PLCC-28 | Intel

The Intel EP610ILC10 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from Altera's EP610 family, housed in a 28-pin PLCC package with a 10ns propagation delay. It delivers pipelined data rates of up to 100 MHz and operates from a single 5V supply (4.75V to 5.25V), making it suitable for high-performance glue-logic and state-machine replacement in 5V legacy systems. A CPLD/EPLD is a non-volatile programmable logic device that retains its configuration without external memory and provides fast, deterministic propagation delays. Within the broader hierarchy, the EP610 sits as: programmable logic -> PLD -> EPLD -> Classic EPLD. It is implemented in CMOS technology, offering low static power consumption compared to bipolar PAL alternatives, and supports both UV-erasable and one-time-programmable (OTP) operation. Key features include 16 macrocells with 16 I/O lines and 4 dedicated inputs, 160 product terms, a 15ns pin-to-pin propagation delay (tPD), and a 100 MHz maximum internal clock frequency. The PAL-type AND-OR-NOT architecture with user-configurable macrocell flip-flops allows implementation of registered or combinatorial logic. The I-suffix indicates the industrial operating temperature range of -40C to +85C. The EP610ILC10 uses a classic sum-of-products architecture with a programmable AND array feeding fixed OR terms, followed by individually configurable output macrocells. Each macrocell contains a flip-flop and programmable output polarity, supporting D, T, JK, and SR flip-flop modes. The device is programmed via the Altera programming algorithm using a master programming unit, with security bit support to protect design IP. Typical applications include address decoding for microprocessor systems, bus interface glue logic, state-machine replacement, peripheral control, and 5V industrial control boards. The 100 MHz performance makes it useful in video timing and data-path control where fast, predictable logic is needed. When designing, note that the EP610 is a mature, NRND/EOL part - verify lifetime-buy status with the distributor before committing to new designs. The 28-pin PLCC package requires a through-hole or socketed footprint, so plan board layout accordingly. This page synthesizes distributor pricing, Classic EPLD family variants, and practical 5V glue-logic design notes not found in the original datasheet.

견적 요청 문의하기
EP610ILI-12 - 300-Gate Classic EPLD, 12ns, PLCC-28 | Altera
EP610ILI-12

EP610ILI-12 - 300-Gate Classic EPLD, 12ns, PLCC-28 | Altera

The Altera EP610ILI-12 is a 300-gate Classic EPLD from the EP610 family, packaged in a 28-pin Plastic J-Lead Chip Carrier (PLCC) and specified with a 12 ns pin-to-pin propagation delay. It provides 16 macro cells and operates from a single 5 V supply, drawing classic CMOS standby current in the I-grade industrial temperature range. Classic EPLDs (Erasable Programmable Logic Devices) are non-volatile programmable logic ICs that use EPROM/EEPROM cells to store the fuse map. They sit below modern CPLDs and FPGAs in the programmable logic hierarchy (PAL/GAL < Classic EPLD < MAX CPLD < FPGAs), and are intended for glue-logic, address decoding, state-machine and bus-arbiter functions where deterministic 12 ns timing and zero-config boot are required. Key features of the EP610ILI-12 include 300 usable gates, 16 macro cells, 4 dedicated inputs, a programmable security bit for proprietary design protection, 100% generically tested TTL-compatible I/O, and in-system 100% test coverage. The 12 ns speed grade (the "-12" suffix) places it in the mid-tier of the EP610 family, which spans from -10 to -25 speed grades. The "I" indicates the industrial temperature grade and "L" denotes low-power CMOS operation. Typical applications include TTL glue-logic replacement, address decoding for 8/16-bit microprocessors, state-machine controllers, bus arbitration, and legacy 5 V industrial control designs. Because the EP610 family is mature and now positioned as a legacy part, EP610ILI-12 is frequently specified for maintenance of existing equipment rather than new greenfield designs. When designing with this device, program it with a Classic EPLD programmer or compatible third-party tool (e.g. Altera MAX+PLUS II legacy flow). Note that Altera's PLCC package follows JEDEC MO-047 outlines and the JEDEC EEPROM cell retention spec applies for the user-programmable fuse map.

견적 요청 문의하기
EP610IPC-10 - Classic EPLD 16-Macrocell 10ns OTP PLD | Altera
EP610IPC-10

EP610IPC-10 - Classic EPLD 16-Macrocell 10ns OTP PLD | Altera

The Altera EP610IPC-10 is a UV-Erasable/OTP (One-Time Programmable) member of the Altera Classic EPLD family, delivering 16 macrocells and 300 usable gates in a 24-pin plastic DIP (PDIP) package. Per the manufacturer datasheet, the part provides a propagation delay of 15 ns (the -10 speed grade is the tPD-10 bin) and supports system clock operation up to 100 MHz, making it a long-standing workhorse for glue-logic, state-machine, and bus-interface integration. What is a Classic EPLD? An Erasable Programmable Logic Device (EPLD) is a CMOS-based programmable logic IC that combines PAL/GAL-style AND/OR arrays with a configurable output macrocell. EPLDs sit between simple PLDs (PALs/GALs, typically tens of gates) and complex PLDs (CPLDs/FPGAs, thousands of gates). Classic EPLDs from Altera pioneered the integration of multiple PAL-equivalent functions plus buried registers into a single 24- or 28-pin DIP, allowing engineers to replace four to six discrete 20-pin PALs with one part. The EP610 is the smallest Classic family member with 16 macrocells; its siblings EP910 (24 macrocells) and EP1810 (48 macrocells) extend the architecture for larger designs. Key features include 16 macrocells, 16 dedicated input pins (4 dedicated inputs plus 12 I/O), 20 total input pins, 160 product terms, a Turbo-only AND-OR-NOT architecture, JTAG-free ISP (programmed via an Altera Master Programming Unit or compatible third-party programmer), and 5 V CMOS/TTL-compatible I/O. Per the Classic EPLD datasheet, the device supports 100% TTL emulation and integrates cleanly with standard 74LS/74F logic families. The 24-pin PDIP form factor is friendly to through-hole prototyping and legacy system retrofits. From a technical-depth perspective, the EP610 uses a CMOS EEPROM/UV-EPROM cell technology with a programmable interconnect array feeding a sum-of-products logic matrix. Each macrocell contains a flip-flop, output enable polarity, and feedback path to the AND array, allowing D/T/JK flip-flop and combinatorial outputs to coexist in the same device. The I pin suffix denotes the industrial operating temperature range (-40C to +85C) and ceramic-windowed (UV-erasable) package, while the C suffix indicates plastic OTP. The -10 suffix indicates the 10 ns commercial tPD grade. Typical applications include bus-interface bridging (e.g., replacing multiple 74LS245/74LS373 glue-logic chips with one EP610), state-machine controllers in industrial automation, address decoding and wait-state generation in 80C186/68k/MIPS embedded systems, and legacy telecom backplane glue-logic. The 24-pin PDIP package is particularly valued in long-lifecycle industrial, military, and aerospace systems that prefer through-hole components for field-serviceability. When designing with the EP610IPC-10, plan for programming infrastructure: the part requires either a UV eraser window (I grade) or one-time-programmable configuration (C grade, no window), plus an Altera-compatible device programmer. Engineers migrating new designs should also evaluate the MAX II or MAX V CPLD families as modern, in-system-programmable alternatives with longer supply continuity. This page synthesizes current distributor availability, parametric-equivalent drop-in alternatives, and design notes not found in the original Classic EPLD datasheet, helping engineers source, second-source, and qualify the EP610IPC-10 for both new designs and legacy field-replacements.

견적 요청 문의하기
EP610IPC-25 - 25ns Classic EPLD, 20 I/O, 5V CMOS | Intel/Altera
EP610IPC-25

EP610IPC-25 - 25ns Classic EPLD, 20 I/O, 5V CMOS | Intel/Altera

The Intel (formerly Altera) EP610IPC-25 is a Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, offering a PAL-type architecture implemented in advanced CMOS technology. It provides 25 ns pin-to-pin propagation delay, supports up to 20 inputs and 16 macrocell outputs, and contains 160 product terms for logic integration. The device operates from a single 4.75V to 5.25V supply and is rated for commercial temperature operation from 0°C to 70°C, packaged in a 24-pin plastic DIP (PDIP-24). A Classic EPLD is an early-generation programmable logic device that combines multiple PAL (Programmable Array Logic) and GAL (Generic Array Logic) functions into a single erasable, reprogrammable IC fabricated in CMOS. EPLDs sit in the hierarchy between simple PLDs (PALs/GALs) and modern FPGAs/CPUs - they offer non-volatile, in-system reprogrammable logic that integrates glue logic, state machines, address decoding, and bus interfacing on a single chip. The EP610 family was one of Altera's foundational product lines in the 1980s and remains in service for legacy industrial, military refresh, and long-lifecycle equipment designs. Key features of the EP610IPC-25 include 100% TTL emulation of standard 10K/100K ECL and 74LS logic functions, macrocell-based output architecture with configurable registered or combinatorial outputs, and on-chip erasable CMOS memory for in-system reprogrammability. The device supports multiple package options across the family and is JEDEC-standard pinout compatible within the EP610 series, enabling drop-in speed-grade and temperature-grade substitution. The architecture combines a programmable AND/OR array with dedicated output macrocells, allowing designers to replace dozens of 74LS TTL gates with a single chip. This density advantage, combined with CMOS power consumption (typically under 200 mW active), made the EP610 family a workhorse for industrial control, telecommunications glue logic, and legacy computing systems. The 'IPC-25' suffix denotes the 24-pin plastic DIP package with a 25 ns speed grade. Typical applications include address decoding and bus interfacing in 8086/68000-based embedded systems, glue logic integration in telecommunications equipment, state machine implementation in industrial controllers, and legacy TTL/74LS logic replacement. The wide supply tolerance (4.75V-5.25V) makes it tolerant of unregulated 5V rails commonly found in industrial backplanes. When designing with this device, verify that the 25 ns propagation delay meets your critical timing path requirements - the EP610 family is offered in speed grades from 15 ns to 35 ns. Note that this is an OTP (one-time programmable) windowless plastic package; for prototyping or development use the CERDIP/UV-erasable variants (EP610DC/EP610DM). This page synthesizes distributor pricing, same-family speed-grade alternatives, and practical design notes for the EP610IPC-25 that go beyond the manufacturer datasheet.

견적 요청 문의하기
EP610JI-30 - 16-Macrocell Classic EPLD, 30ns, CQCC28 Windowed | Altera
EP610JI-30

EP610JI-30 - 16-Macrocell Classic EPLD, 30ns, CQCC28 Windowed | Altera

The Altera EP610JI-30 is a high-performance, 16-macrocell Classic EPLD (Erasable Programmable Logic Device) from the EP610 family, housed in a 28-pin windowed ceramic JLCC (CQCC28) package and rated for a 30 ns propagation delay. It operates from a single 5 V supply using CMOS PAL-type architecture, with 4 dedicated inputs, 16 I/O lines, and 160 product terms driven by two external clocks, supporting pipelined data rates up to 100 MHz. A Classic EPLD (Erasable Programmable Logic Device) is a UV-erasable member of the programmable logic family, sitting between simple PAL/GAL devices and modern CPLDs/FPGAs in the design complexity hierarchy (PAL/GAL -> Classic EPLD -> MAX CPLD -> FPGA). The windowed ceramic package contains a quartz window that allows the device's internal EPROM configuration memory to be erased with ultraviolet light, enabling hundreds of reprogramming cycles during prototyping and design iteration. The 16-macrocell Classic architecture is sum-of-products based, with a global bus interconnecting the AND/OR arrays to a programmable output macrocell register bank. Key features of the EP610JI-30 include the 32 ns propagation delay window (often marketed as 30 ns grade per the speed suffix), 100 MHz pipeline throughput, JTAG-free boundary-scan-free classic programming via the Altera programming algorithm, and 5 V CMOS I/O. The device supports bidirectional I/O, programmable output enables, and registers on every macrocell, making it a flexible glue-logic replacement for discrete TTL/CMOS gate arrays in legacy designs. Two clock inputs feed the device's internal register clock network. The EP610 architecture uses an EPROM-based sum-of-products structure with a programmable interconnect array feeding 16 output macrocells. Each macrocell contains a programmable flip-flop, output polarity selection, and tri-state control. This architecture gives deterministic tpd that does not depend on routing congestion, a major advantage over early FPGA architectures of the same era, and the part supports synchronous and asynchronous clocking schemes with predictable pin-to-pin timing. Typical applications for the EP610JI-30 include legacy bus-interface glue logic, address decoding for M68000/i8086 systems, state-machine replacement in industrial controllers, TTL/CMOS gate-array consolidation, and prototyping of glue logic where modern FPGAs are not required. The windowed package is specifically chosen for engineering development and low-volume production where in-house UV erasure and reprogramming provide the lowest total cost. When designing with this part, note that the EP610 requires an Altera-compatible programmer (e.g., Altera Logic Programmer or third-party equivalents). Decoupling must use a 0.1 microfarad ceramic capacitor per VCC pin placed within 5 mm of the package. Inputs float when not driven; tie unused inputs to VCC or GND through a 10 kohm resistor to avoid CMOS shoot-through current. This page synthesizes distributor stock status, JLCC28 package diagrams, and pin-compatible Classic EPLD alternatives not consolidated in the original Altera datasheet, helping sourcing engineers extend the lifecycle of legacy Classic EPLD designs.

견적 요청 문의하기
EP610LC-15 - 16-Macrocell Classic EPLD, 15ns PLCC-28 | Altera
EP610LC-15

EP610LC-15 - 16-Macrocell Classic EPLD, 15ns PLCC-28 | Altera

The Altera EP610LC-15 is a high-performance, 16-macrocell Classic EPLD (Erasable Programmable Logic Device) housed in a 28-pin PLCC package with a 15 ns propagation delay and pipelined data rates up to 100 MHz. This CMOS-era Erasable Programmable Logic Device (EPLD) integrates 300 usable gates and 16 macrocells into a deterministic, non-volatile logic fabric, making it a foundational part for glue-logic integration in 5 V industrial systems. The device supports in-system UV-erase (windowed versions) and one-time-programmable (OTP) configurations, with -15 speed grade delivering 15 ns pin-to-pin delay. An EPLD (Erasable Programmable Logic Device) is a non-volatile programmable logic device that pre-dates modern FPGAs and CPLDs. In the taxonomy, an EPLD sits between a PAL (Programmable Array Logic) and a modern CPLD/FPGA: like a PAL, it is non-volatile and instant-on, but like a modern CPLD it contains multiple macrocells with sum-of-products logic and a fixed interconnect. The Classic EPLD family from Altera was widely adopted in the 1980s and 1990s as a higher-density, faster alternative to discrete PAL/GAL devices for state machines, address decoding, and bus-interface logic. Key features of the EP610LC-15 include 16 macrocells with 16 dedicated flip-flops, propagation delays of 15 ns, fmax of 83.3 MHz counter frequency (and pipelined throughput up to 100 MHz), 24 input pins, and 16 output pins in the J-lead PLCC-28 footprint. The device operates from a single 5 V supply and is fabricated in CMOS technology, providing low static power consumption compared to bipolar PALs of the same era. Architecturally, the EP610LC-15 uses a sum-of-products (AND-OR) plane feeding configurable macrocell flip-flops, with a global interconnect that guarantees deterministic, predictable timing - critical for synchronous state-machine design. This deterministic timing, plus non-volatile configuration, makes Classic EPLDs preferred over early FPGAs in safety- and timing-critical industrial applications. The device is currently maintained by Rochester Electronics, LLC as an authorized Altera licensee for long-lifecycle programs. Typical applications include bus-interface glue logic, address decoding and chip-select generation, state-machine controllers, and replacement of discrete 74LS/74F TTL logic in 5 V systems. The wide operating voltage (single 5 V) and PLCC footprint also made it a common choice in industrial control, telecommunications backplane, and military/aerospace programs where long-term supply continuity is mandatory. When designing with this device, note that programming requires a compatible EPROM/UV eraser and programmer (e.g., Data I/O or BP Microsystems), and design entry is typically performed with classic Altera MAX+PLUS II or equivalent tools. Designers should also verify available package alternatives (windowed ceramic vs. plastic OTP) before committing to a long-lifecycle design. This page synthesizes Rochester Electronics distributor pricing, same-family Altera Classic drop-in alternatives, and practical design notes for long-lifecycle EPLD programs - information not consolidated in any single manufacturer datasheet.

견적 요청 문의하기
EP610LC-25 - 16-Macrocell Classic EPLD, 25ns, PLCC-28 | Intel
EP610LC-25

EP610LC-25 - 16-Macrocell Classic EPLD, 25ns, PLCC-28 | Intel

The Intel EP610LC-25 is a 16-macrocell CMOS Classic EPLD (Erasable Programmable Logic Device) with a 25 ns propagation delay, housed in a 28-pin PLCC package. It is part of Altera's original Classic EPLD family, designed for high-performance glue-logic replacement of discrete TTL and PAL/GAL devices in 5V systems. The device delivers pipelined data rates of up to 100 MHz and offers 16 macrocells organized into four Logic Array Blocks (LABs), each containing four macrocells. A Classic EPLD is a type of programmable logic device (PLD) that combines the low cost and simplicity of PAL/GAL architectures with the flexibility and density of early FPGA-like logic. In the broader taxonomy, the EP610LC-25 sits within: programmable logic device -> erasable PLD -> CMOS EPLD -> Classic EPLD family. The EP610 family was introduced in the late 1980s as one of the first UV-erasable CMOS PLDs suitable for high-speed state machine and bus-interface applications. Key features include 16 macrocells, 25 ns maximum pin-to-pin propagation delay (tPD), a 100 MHz maximum toggle frequency, and a 5V ±5% supply requirement. The device is in-system or window-erasable (UV forcerasable ceramic windowed variants) and supports industry-standard JEDEC file formats for programming. Per the Altera Classic Device Family datasheet, the EP610 provides bidirectional I/O, programmable output enable, and configurable flip-flop polarity in every macrocell. The architecture uses an AND/OR PLA-style logic array with a fixed OR plane feeding programmable flip-flop macrocells, providing predictable timing with no routing delay variance. Each macrocell contains a flip-flop, output polarity control, and a tri-state output buffer, enabling implementation of both combinatorial and registered logic with deterministic timing. Typical applications include bus-interface glue logic, state-machine controllers, address decoders, and 5V legacy system replacements. The 28-pin PLCC footprint is socket-compatible with standard 28-pin PLCC sockets, enabling easy drop-in replacement of older PAL/GAL devices. When designing with this part, designers should ensure 5V ±5% supply tolerance and provide adequate decoupling (100 nF ceramic near VCC). For new designs, modern CPLDs such as the Altera MAX II family or Lattice ispMACH 4000 series offer substantially higher logic density, lower power, and in-system programmability. This page synthesizes distributor availability, pin-compatible alternatives from the same Classic EPLD family, and practical design notes not found in the manufacturer datasheet.

견적 요청 문의하기
EP610LC-30 - 16-Macrocell Classic EPLD, 30ns, 5V | Altera / Intel
EP610LC-30

EP610LC-30 - 16-Macrocell Classic EPLD, 30ns, 5V | Altera / Intel

The Altera (Intel) EP610LC-30 is a 16-macrocell Classic Erasable Programmable Logic Device (EPLD) from the EP610 family, offered in a 24-pin ceramic or plastic DIP/Cerdip package with a 30 ns pin-to-pin propagation delay and 5 V CMOS supply operation. It is built on an advanced CMOS EPROM process that combines high-speed logic integration with low static power consumption and supports pipelined data rates of up to 100 MHz for high-performance glue-logic replacement. A Classic EPLD is a non-volatile programmable logic device sitting in the hierarchy of simple PLDs -> EPLD/CPLD -> programmable logic -> semiconductor. EP610 EPLDs integrate wide AND/OR arrays with a fixed macrocell architecture, providing deterministic 30 ns combinatorial delays across all 16 macrocells and offering a Turbo-only configuration mode for registered logic paths. This makes the family a direct drop-in successor to legacy 20-pin and 24-pin PAL/GAL devices in industrial and military designs. Key features include 16 macrocells, 5 V single-supply operation (VCC = 4.75 V to 5.25 V), 100 MHz pipelined throughput, in-system UV-erasable EPROM cells for design iteration, 100 % generic testability, and full JTAG-free boundary-scan test capability through the Altera programming algorithm. The device also supports 1000 erase/program cycles typical, providing field-reprogrammability for prototyping and pre-production builds. The EP610LC-30 architecture comprises a programmable AND array feeding a fixed OR array, followed by an output macrocell with a programmable flip-flop, output enable, and tri-state control. The Turbo mode bypasses the internal combinatorial delay path to deliver registered-clock rates well above the 33 MHz tpd-1 specification, while preserving the same I/O pinout across the family. Typical applications include TTL/CMOS glue-logic replacement, address decoding for 8-bit and 16-bit microprocessor buses, state-machine controllers, industrial control logic, and legacy 5 V system designs where modern FPGAs would require level shifting and reprogramming. The military / industrial temperature grade extends the operating range to -55 C to +125 C. When designing with the EP610LC-30, ensure that VCC decoupling (0.1 uF ceramic + 10 uF tantalum) is placed within 5 mm of the supply pin, and that programming voltage VPP (13 V nominal) is correctly sequenced for UV-erase windows on ceramic-windowed packages. Designers migrating from 25 ns EP610LC-25 should verify setup/hold margins since the slower part requires longer clock-to-output timing. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, helping sourcing engineers validate second-source decisions for legacy 5 V EPLD sockets.

견적 요청 문의하기
EP610LC-35 - 16-Macrocell Classic EPLD, 37ns, 5V, PLCC-35 | Altera
EP610LC-35

EP610LC-35 - 16-Macrocell Classic EPLD, 37ns, 5V, PLCC-35 | Altera

The Altera EP610LC-35 is a Classic-series Erasable Programmable Logic Device (EPLD) from the EP610 family, delivering 16 macrocells, 300 usable gates, and a 37 ns propagation delay in a 28-pin plastic J-lead chip carrier (PLCC) package. It operates from a single 5 V supply and is fabricated in CMOS technology for low power consumption. A Classic EPLD is a non-volatile programmable logic device that combines the integration of a PLD with erasable CMOS architecture, sitting in the hierarchy between discrete 22V10-style SPLDs and modern SRAM-based FPGAs. The EP610 family targets glue-logic replacement, state-machine implementation, and decoder/encoder functions in 5 V systems where a small number of logic functions must be implemented in a single package. Key features include 24 dedicated input pins, 16 output macrocells, 4 combinatorial feedback paths per macrocell, programmable I/O architecture, and a synchronous prescaler for flexible clock division. The Classic family supports 100% factory-tested AC and DC specifications with on-board logic-test circuitry that enables standard production-flow verification. Macrocells share a sum term and product term, allowing wide-input AND/OR functions to be combined with registered outputs. The EP610 uses CMOS EEPROM-based configuration cells backed by UV-erasable windowed ceramic variants (EP610I/J) and one-time-programmable plastic variants (EP610L/D). Architecture-wise, every macrocell contains a flip-flop, an output enable, and feedback into the AND-array, supporting both registered and combinatorial outputs from the same physical pin. The 37 ns tpd speed grade (-35) is the slowest of the EP610 family and trades timing margin for slightly lower dynamic current draw at lower toggle rates. Typical applications include 5 V bus decoding, address mapping for microcontroller and 8-bit/16-bit processor systems, state-machine controllers, glue-logic consolidation in industrial control boards, and replacement of legacy 22V10 PAL/GAL devices. The wide supply tolerance makes it usable in 5 V-only industrial backplanes where modern 3.3 V-only CPLDs are not pin-compatible. When designing with this part, note that the -35 speed grade is the slowest EP610 variant; verify timing margins carefully when porting -25 or -15 designs. Programming is performed via the Altera MAX+PLUS II development system and a hardware programmer; source files are still maintained in the Altera Classic Device Family support archive. This page synthesizes distributor pricing, Rochester Electronics stock status, same-family speed-grade and package alternatives, and practical design notes that go beyond the marketing blurb in the original datasheet.

견적 요청 문의하기
EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester
EP610LC15

EP610LC15 - 16-Macrocell Classic EPLD, 15ns, 5V, PLCC-28 | Rochester

The Rochester Electronics EP610LC15 is a 16-macrocell Classic EPLD (Erasable Programmable Logic Device) with a 15 ns propagation delay, supplied in a 28-pin PLCC package and fabricated on a 5V CMOS process with UV-erasable windowed ceramic package option. The Classic family provides glue-logic integration at pipelined data rates of up to 100 MHz and is fully compatible with the original Altera Classic EPLD architecture that defined the segment in the late 1980s. A CPLD/EPLD is a non-volatile programmable logic device that combines multiple PAL-style macrocell arrays on a single die, allowing designers to replace dozens of 74-series SSI/MSI glue-logic packages with a single erasable part. EPLDs sit in the broader taxonomy programmable logic device (PLD) -> EPLD/CPLD -> CMOS programmable logic -> digital semiconductor, and historically predate modern flash-based CPLDs and SRAM-based FPGAs. The Classic architecture uses a sum-of-products AND-OR array followed by an output macrocell with selectable flip-flop polarity, making it well suited for state machines, address decoding, and bus interface logic. Key features of the EP610LC15 include 16 macrocells, 10 dedicated inputs, 16 I/O pins forming a 24-pin logic array, a 15 ns pin-to-pin propagation delay (tPD), a 83.3 MHz maximum toggle frequency, and a single 5V (±10%) supply with TTL-compatible I/O. The device is in-system programmable via the Altera-standard 4-pin JTAG-style serial interface and supports security-bit protection to lock the programmed pattern. The EP610 architecture uses an EPROM-based AND array driving a fixed OR array, with each macrocell containing a programmable flip-flop, output enable, and feedback path. The 5V CMOS process yields zero standby current on disabled outputs and typical quiescent current in the low milliamp range, while the ceramic-windowed package allows pattern erasure under UV light for prototyping and design iteration. Typical applications include bus decoding for 8086/68000 microprocessor systems, address decoding for memory and peripheral mapping, state-machine implementation in industrial controllers, and TTL-to-CMOS level-interface bridging in legacy 5V designs. The 83.3 MHz fMAX also supports small pipelined datapath functions such as counter chains, frequency dividers, and shift registers. When designing with the EP610LC15, observe that the LC suffix denotes the commercial 0°C to +70°C operating range and the 15 ns speed grade; the -15 speed bin is the slowest of the EP610 family and should be selected only when timing slack allows. Programming requires a hardware programmer supporting the Classic EPLD algorithm (e.g., Altera PL-ASAP or Data I/O). Lead-finish options are matte-tin over nickel (lead-free) per modern Rochester Electronics re-creation, RoHS compliant. This page consolidates Rochester Electronics and Altera datasheet specs, cross-brand 5V-CPLD drop-in candidates, and design notes for legacy 5V glue-logic replacement that distributor listings do not present in one place.

견적 요청 문의하기