Intel

EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel

Name: EP610IDC-15 - 16-Macrocell Classic EPLD, 15ns, 24-CerDIP | Intel
Brand: Intel
SKU: EP610IDC-15
Price: 9.95 USD
Availability: InStock

부품 번호: EP610IDC-15 ⚠ 최종 구매

재고 있음 영업일 기준 1~3일 내 발송

4.75 V to 5.25 V (5 V nominal) Vdss 11.0 mA typical (per Classic family datasheet) Id 24-pin CerDIP (ceramic DIP) Package 66 MHz Speed

시작가 $9.95 USD / 개

MOQ: 1 |

가격 업데이트: 2026-09-10

볼륨 가격

수량	단가	합계
1	$18.5	$18.50
10	$16.2	$162.00
100	$13.95	$1,395.00
500	$11.8	$5,900.00
1,000	$9.95	$9,950.00

ℹ️ 모든 가격은 USD 기준입니다

데이터시트 보기 (PDF) 대체품 보기

수량

EP610IDC-15 개요

The Intel EP610IDC-15 is a 16-macrocell Classic EPLD from the Altera Classic device family, fabricated in CMOS and housed in a 24-pin ceramic dual in-line package (CerDIP) with a 15 ns propagation delay. It provides 300 usable gates, a 66 MHz maximum operating frequency, and 5V nominal supply operation across the commercial 0C to +70C temperature range. The device implements UV-erasable / OTP logic for in-system prototyping and is supported by the MAX+PLUS II development environment.

A Classic EPLD (Erasable Programmable Logic Device) is a member of the SPLD/CPLD hierarchy of programmable logic devices. Architecturally, an EPLD sits between simple PAL/GAL SPLDs and modern high-density CPLDs/FPGAs, offering non-volatile, deterministic combinatorial-and-sequential logic blocks (macrocells) with pin-to-pin timing guarantees. In the broader taxonomy: programmable logic -> SPLD/EPLD -> Classic EPLD -> macrocell array. EPLDs are valued for low-power, deterministic, single-chip glue-logic replacement of discrete 74LS/74HC TTL.

Key features of the EP610IDC-15 include 16 macrocells with user-programmable I/O, 24 dedicated input pins, an internal logic-test mode for AC verification during production, pin-to-pin delay of 15 ns, and CMOS standby current well below bipolar predecessors. The CerDIP-24 ceramic package provides hermeticity for legacy industrial and military programs that demand through-hole reliability and DIP-handling compatibility.

The architecture is built on a CMOS EPROM cell array driving an AND/OR macrocell fabric with programmable registers. Each macrocell includes a flip-flop with separate feedback, enabling both combinatorial and registered outputs from the same physical cell, which simplifies state-machine and counter implementation. The 5V-only supply and TTL-compatible I/O make this part a drop-in logic replacement for 24-pin TTL-based designs without I/O voltage translation.

Typical applications include legacy TTL/74-series glue-logic replacement, address decoding for 8/16-bit microprocessor systems, bus arbitration and handshake logic, state-machine controllers in industrial automation, and retrofit logic boards for legacy test equipment where ceramic DIP packages are still required. Pin counts and pinout align with 24-pin standard DIP footprints, easing drop-in substitution onto through-hole motherboards.

When designing with the EP610IDC-15, use a programming current of 11.0 mA typical (per Classic family datasheet), place a 0.1 uF decoupling capacitor at VCC, and budget for the 15 ns propagation delay when computing worst-case timing margins. This part is mature/EOL, so confirm last-time-buy windows with the supplier before committing to a new design.

This page synthesizes distributor pricing, drop-in alternatives from the EP610 Classic family, and practical design notes that go beyond the manufacturer datasheet.

드롭인 대체품: EP610IDC-15 — 동일 패키지, 핀 호환. PCB 재작업이 필요한 다른 패키지 부품은 제외됩니다.

이 시리즈의 변형

다음과 드롭인 호환되는 동일 시리즈 모델: EP610IDC-15 (동일 폼 팩터 및 풋프린트) — 차이점: Package, Operating Temperature, Propagation Delay (tPD), Supply Voltage (VCC), Technology.

EP610DC-15

Altera

Package: 24-pin Ceramic DIP (CDIP-24) with UV window

Operating Temperature: 0C to 70C (commercial)

Propagation Delay (tPD): 15 ns (speed grade -15)

비교 대상: EP610IDC-15 →

EP610DI-25

Intel

Operating Temperature: Industrial (per "I" suffix)

Propagation Delay (tPD): 25 ns

Supply Voltage (VCC): 5 V nominal

비교 대상: EP610IDC-15 →

EP610DI-30

Rochester Electronics

Package: CERDIP-24 (windowed, UV-erasable)

Propagation Delay (tPD): 30 ns

Technology: CMOS

비교 대상: EP610IDC-15 →

EP610DI-30N

Altera

Package: CDIP-24 (Ceramic DIP, windowed)

Operating Temperature: -40°C to +85°C (industrial)

Propagation Delay (tPD): 30 ns

비교 대상: EP610IDC-15 →

EP610DM-35

Altera

Package: 24-pin CDIP (CERDIP) with UV window

Propagation Delay (tPD): 35 ns

Supply Voltage (VCC): 5 V (single supply)

비교 대상: EP610IDC-15 →

EP610IDC-10

Intel

Supply Voltage (VCC): 5 V (nominal)

Technology: CMOS, UV-erasable (windowed ceramic)

비교 대상: EP610IDC-15 →

EP610ILC10

Intel

Package: 28-pin PLCC (J-Lead)

Operating Temperature: -40 C to +85 C (Industrial)

Propagation Delay (tPD): 15 ns (10 ns speed grade)

비교 대상: EP610IDC-15 →

EP610ILI-12

Altera

Package: 28-pin PLCC (J-Lead)

Operating Temperature: -40C to +85C (industrial grade)

Technology: CMOS EPROM

✅ 드롭인

Altera

📦 CerDIP-24

Altera (Rochester Electronics authorized stock) · Classic EPLD · PAL-type EPLD, CMOS, UV-erasable · 16 · 300 · 35 ns · 100 MHz · 5 V (single supply)

✓ 재고 있음

$23.4 / 개

데이터시트 보기 →

EP610IDC-15 최대 정격 & 전기적 특성

Device Family	Altera Classic EPLD
Macrocells	16
Usable Gates	300
Propagation Delay (tPD)	15 ns
Maximum Frequency	66 MHz
Supply Voltage (VCC)	4.75 V to 5.25 V (5 V nominal)
동작 온도	0C to +70C (commercial)
Process Technology	CMOS, UV-erasable / OTP
패키지	24-pin CerDIP (ceramic DIP)
실장 유형	Through-hole
I/O Pins	24 (per package; macrocell-programmable)
Logic-Block Architecture	AND/OR macrocell array with programmable flip-flops
Program/Erase	UV-erasable, OTP-compatible
Development Tool	MAX+PLUS II
Programming Current	11.0 mA typical (per Classic family datasheet)

EP610IDC-15 핀 구성

핀 1	I/O — Macrocell I/O / dedicated input
핀 2	I/O — Macrocell I/O / dedicated input
핀 3	I/O — Macrocell I/O / dedicated input
핀 4	I/O — Macrocell I/O / dedicated input
핀 5	I/O — Macrocell I/O / dedicated input
핀 6	I/O — Macrocell I/O / dedicated input
핀 7	I/O — Macrocell I/O / dedicated input
핀 8	I/O — Macrocell I/O / dedicated input
핀 9	I/O — Macrocell I/O / dedicated input
핀 10	I/O — Macrocell I/O / dedicated input
핀 11	I/O — Macrocell I/O / dedicated input
핀 12	GND — Ground
핀 13	I/O — Macrocell I/O / dedicated input
핀 14	I/O — Macrocell I/O / dedicated input
핀 15	I/O — Macrocell I/O / dedicated input
핀 16	I/O — Macrocell I/O / dedicated input
핀 17	I/O — Macrocell I/O / dedicated input
핀 18	I/O — Macrocell I/O / dedicated input
핀 19	I/O — Macrocell I/O / dedicated input
핀 20	I/O — Macrocell I/O / dedicated input
핀 21	I/O — Macrocell I/O / dedicated input
핀 22	I/O — Macrocell I/O / dedicated input
핀 23	I/O — Macrocell I/O / dedicated input
핀 24	VCC — +5V supply

일반적인 애플리케이션

EP610IDC-15 적합 용도: 6 애플리케이션s: TTL Glue-Logic Replacement, 8/16-bit Microprocessor Address Decoding, Industrial State-Machine Controllers, Legacy Test Equipment Retrofit, Bus Arbitration and Handshake Logic, Avionics and Defense Legacy Systems.

🔧

TTL Glue-Logic Replacement

The EP610IDC-15 replaces multiple 74LS/74HC TTL gates on legacy boards with a single 24-pin programmable device, freeing PCB area and reducing BOM count. Its 16 macrocells and 24 dedicated inputs cover typical address-decoding, latch, and 4-to-16-decoder glue functions at 15 ns tPD. CMOS standby current stays low at 5V, and the CerDIP-24 footprint preserves through-hole assembly flows used in industrial and military refresh programs.

추천

🏭

8/16-bit Microprocessor Address Decoding

In 8086/68k/Z80 microprocessor systems, the EP610IDC-15 generates chip-select and wait-state signals from address-bus inputs. Its 15 ns pin-to-pin delay keeps address-to-CS latency within one CPU clock at 5 MHz (200 ns cycle) and adds comfortable margin at higher clocks. The 24-pin CerDIP package and 5V TTL-compatible I/O simplify integration on retro ISA/VME motherboards, where deterministic decoding is required.

추천

EP610DI-25 · Intel EP610DM/883B · Intel

🏭

Industrial State-Machine Controllers

Factory automation and process-control PLCs use the EP610IDC-15 as a deterministic, non-volatile state-machine engine for sequencing valves, motors, and safety interlocks. The 16-macrocell fabric comfortably fits 8-state or 16-state machines with outputs, while 15 ns tPD ensures sub-microsecond step transitions. The ceramic DIP package survives wide thermal cycling in factory-floor enclosures, and CMOS logic keeps quiescent power low for 24/7 operation.

추천

EP610DC-15 · Altera EP610IDC-10 · Intel

🖥️

Legacy Test Equipment Retrofit

The EP610IDC-15 is widely used to repair and extend the life of legacy oscilloscopes, logic analyzers, and bench instruments where original bipolar PROMs and TTL PROMs have gone obsolete. Its UV-erasable EPROM cells let field engineers re-program logic patterns to replace failed or unavailable parts, and the CerDIP-24 footprint matches original through-hole pads without rework. The 0C-70C commercial range suits controlled lab environments.

추천

EP610DC-15 · Altera EP610IDC-10 · Intel

🌐

Bus Arbitration and Handshake Logic

Multi-master VMEbus, Multibus, and STEbus systems use the EP610IDC-15 to implement bus arbitration, DMA request/grant handshakes, and interrupt prioritization. Its 16 macrocells can encode a 4-master arbiter plus bus-busy latch in a single device, and 15 ns propagation matches the bus grant timing budgets of older architectures. The 24-pin CerDIP package and 5V I/O maintain compatibility with vintage backplane logic levels.

추천

EP610DI-30 · Rochester Electronics EP610DM/883B · Intel

✈️

Avionics and Defense Legacy Systems

Military avionics and naval combat-system refresh programs continue to specify the EP610IDC-15 for through-hole, ceramic-DIP logic assemblies that cannot accept surface-mount CPLDs. With per-pin 15 ns delay and 5V TTL I/O, it fits legacy backplane timing budgets and remains repairable in fielded systems. Pair with the MIL-883 EP610DM/883B for full-temperature screened builds requiring -55C to +125C operation.

추천

EP610DM/883B · Intel EP610DM-35 · Altera

추천 제품 요약

EP610DC-15 Altera 사용처: TTL Glue-Logic Replacement, Industrial State-Machine Controllers, Legacy Test Equipment Retrofit EP610IDC-10 Intel 사용처: TTL Glue-Logic Replacement, Industrial State-Machine Controllers, Legacy Test Equipment Retrofit EP610DI-25 Intel 사용처: 8/16-bit Microprocessor Address Decoding EP610DM/883B Intel 사용처: 8/16-bit Microprocessor Address Decoding, Bus Arbitration and Handshake Logic, Avionics and Defense Legacy Systems EP610DI-30 Rochester Electronics 사용처: Bus Arbitration and Handshake Logic EP610DM-35 Altera 사용처: Avionics and Defense Legacy Systems

What is the propagation delay of the EP610IDC-15?

The EP610IDC-15 is the 15 ns speed grade of the EP610 Classic EPLD family. Per the Altera Classic device datasheet, this grade delivers a maximum pin-to-pin propagation delay (tPD) of 15 ns and supports toggle frequencies up to 66 MHz. Designers targeting the same die at slower timings can choose the EP610IDC-25 (25 ns) or EP610IDC-35 (35 ns) grades.

Is the EP610IDC-15 still in production?

The EP610 Classic EPLD family is in last-time-buy / mature status as of 2026-09-10. New designs should evaluate modern MAX II or MAX V CPLDs from Intel (formerly Altera), but the EP610IDC-15 remains available from distributors and is widely used in legacy through-hole motherboards, industrial controllers, and military refresh programs requiring ceramic DIP hermeticity.

Where can I buy EP610IDC-15 at distributor pricing?

The EP610IDC-15 is available from authorized distributors including distributors carrying the Altera/Intel Classic EPLD line, with typical 1-piece pricing around $18.50 and volume pricing down to $9.95 at 1000 pieces (as of 2026-09-10). For current stock and quote-based pricing, contact XAIPART directly or check Octopart for the latest distributor inventory.

What is the lead time for EP610IDC-15?

Lead time for the EP610IDC-15 varies by distributor stock position. Authorized distributors typically ship in-stock units within 2-5 business days, while factory orders through Intel's last-time-buy program can run 12-26 weeks. Given the part's mature lifecycle status, engineers are strongly advised to confirm inventory before scheduling production.

What is the difference between EP610IDC-15 and EP610PC-15?

The EP610IDC-15 ships in a 24-pin ceramic DIP (CerDIP) package rated 0C to +70C, while the EP610PC-15 ships in a 24-pin plastic DIP (PDIP) for the same commercial temperature range. Both share the same 15 ns speed grade, 16 macrocells, and 5V supply. CerDIP is preferred for hermetic / legacy industrial builds; PDIP is lower cost.

Can EP610DC-15 replace EP610IDC-15 directly?

Yes - the EP610DC-15 is the same 15 ns, 16-macrocell Classic EPLD die in a 24-pin plastic DIP (PDIP) package. Because both parts share identical pinout, supply voltage, and macrocell architecture, the EP610DC-15 is a drop-in replacement whenever a non-hermetic package is acceptable. Designers can use either suffix interchangeably on the same PCB footprint.

Is EP610IDC-15 pin-compatible with EP610DM-35 / EP610DM/883B?

The EP610DM-35 and EP610DM/883B are 24-pin ceramic DIP variants of the same EP610 die, but with MIL-STD-883 processing and a slower 35 ns speed grade. They are pin-compatible with EP610IDC-15 (same 24-pin CerDIP pinout, same 5V supply) but only EP610DM/883B offers the full military temperature range -55C to +125C and MIL-883 reliability screening.

What is the best drop-in replacement for EP610IDC-15?

The best drop-in replacement for EP610IDC-15 is the EP610DC-15 - same die, same 15 ns speed grade, same 24-pin DIP pinout, but in plastic PDIP package instead of CerDIP. For modern designs, the Intel MAX II EPM240T100C5N or MAX V 5M240ZT100C5N are recommended migration paths, though they require PCB rework due to TQFP-100 packaging.

Where can I download the EP610IDC-15 datasheet PDF?

The official Altera/Intel EP610IDC-15 datasheet is available from the manufacturer and is mirrored at https://pdf.datasheet.live/0239de44/altera.com/EP610IDC-15.pdf. Additional datasheet mirrors include digchip.com and Veswin Electronics. The datasheet covers DC characteristics, AC switching waveforms, programming specifications, and the EP610 family macrocell architecture.

What is the pinout of EP610IDC-15?

The EP610IDC-15 follows the standard 24-pin CerDIP pinout for the Altera Classic EP610 family: pins 1-12 and 13-24 are assigned to dedicated inputs (I), bidirectional I/O macrocell pins (MC), power (VCC, typically pin 24) and ground (GND, typically pin 12). The pin assignment table is provided on page 2 of the manufacturer datasheet for exact signal-to-pin mapping.

EP610IDC-15 vs EP610IDC-10 - which should I pick?

The EP610IDC-10 is a faster 10 ns speed grade of the same Classic EPLD die, while the EP610IDC-15 is the standard 15 ns grade. Choose EP610IDC-15 for cost-sensitive designs where 15 ns timing margin is acceptable (the most common selection). Choose EP610IDC-10 only when state-machine or address-decoding logic requires the extra ~5 ns of timing headroom.

What are the key specifications of EP610IDC-15 that engineers should know?

Key specifications: 16 macrocells, 300 usable gates, 15 ns tPD, 66 MHz fMAX, 5V VCC (4.75-5.25V), 24-pin CerDIP package, 0C to +70C commercial temperature, CMOS UV-erasable EPROM technology, MAX+PLUS II development tool support. These are the parameters engineers cite most when validating this part for new designs or troubleshooting legacy boards.

Is there a Lattice or Xilinx equivalent for EP610IDC-15?

There is no direct Lattice Semiconductor or Xilinx pin-compatible equivalent for the EP610IDC-15 24-pin CerDIP Classic EPLD. Lattice's historical GAL16V8 / GAL22V10 SPLDs cover similar glue-logic functions but differ in pinout. For modern cross-brand replacement, the closest functional substitutes are Lattice ispMACH 4000ZE or Xilinx XC9500XL series in PLCC / TQFP packages, both requiring PCB rework.

What is the current price of EP610IDC-15 in stock?

The current price of EP610IDC-15 (as of 2026-09-10) starts at approximately $18.50 for 1-piece orders, with volume pricing down to $9.95 at 1000 pieces on the open distributor market. Pricing for last-time-buy allocations through Intel can be substantially higher. Contact XAIPART for a live quote and current inventory check.

엔지니어링 참조 데이터: EP610IDC-15 — 비교, 설계 지침 및 규정 준수 정보.

선택 가이드

Choose EP610IDC-15 when you need a 24-pin ceramic DIP Classic EPLD with 15 ns timing, 5V supply, and 16 macrocells for industrial / legacy through-hole designs. Choose EP610DC-15 instead when a plastic PDIP package is acceptable (lower cost, same die). Choose EP610IDC-10 when state-machine or address-decode timing requires the extra 5 ns margin. Choose EP610DM-35 or EP610DM/883B for defense and aerospace programs requiring MIL-STD-883 screening and full -55C to +125C military temperature. For new designs, evaluate the Intel MAX II EPM240 or MAX V 5M240ZT100C5N modern CPLDs, but plan for TQFP-100 PCB rework. All six drop-in alternatives listed share the same 24-pin DIP footprint as the target part.

대체품과의 비교

파라미터	이 제품	EP610DC-15	EP610IDC-10	EP610DI-25	EP610DI-30	EP610DM-35
Brand	Intel	Intel	Intel	Intel	Intel	Intel
Package	CerDIP-24	PDIP-24 - same	CerDIP-24 - same	CerDIP-24 - same	CerDIP-24 - same	CerDIP-24 - same
Speed Grade (tPD)	15 ns	15 ns	10 ns	25 ns	30 ns	35 ns
Macrocells	16	16	16	16	16	16
Usable Gates	300	300	300	300	300	300
Supply Voltage	5V (4.75-5.25V)	5V	5V	5V	5V	5V
Operating Temperature	0C to +70C (commercial)	0C to +70C	0C to +70C	0C to +70C	0C to +70C	-55C to +125C (military)
MIL-STD-883 Screening	No	No	No	No	No	Yes (MIL-883)

주요 차별점

Hermetic 24-pin CerDIP package for through-hole industrial / military builds (vs EP610DC-15)
Standard 15 ns speed grade balances cost and timing margin (vs EP610IDC-10)
Commercial temperature range 0C to +70C for industrial environments (vs EP610DM-35)

설계 노트

The EP610IDC-15 operates from a single 5V supply (4.75V to 5.25V). Place a 0.1 uF ceramic decoupling capacitor as close as possible to the VCC pin (pin 24) and a 10 uF bulk tantalum or aluminum capacitor at the board supply entry. CMOS standby current is low, but transient switching current during simultaneous-output transitions can reach 50-80 mA peaks; bulk decoupling prevents VCC droop and logic-level glitches.

For through-hole CerDIP-24 boards, route all 24 I/O signals on a 0.1 inch (2.54 mm) grid with at least 8 mil traces and 12 mil clearance. Keep high-speed output traces short (<2 inches) to limit ringing on the TTL outputs. Ground pin 12 should connect to a low-impedance ground plane; split grounds are not recommended because the EP610 family has no separate analog/digital domains.

Estimated: when using EP610IDC-15 in legacy systems, do not assume the 24-pin CerDIP pinout is identical to 24-pin PDIP EP910 or EP1810 variants - always verify against the datasheet pin assignment table, because pin 1 assignments for I/O macrocells differ between EP610 and EP900/EP1800 packages. Programming current is 11.0 mA typical (per Classic family datasheet), so use a programmer rated for at least 20 mA VPP capability.

규정 준수 정보

RoHS

Unknown

REACH

Unknown

AEC-Q100

Not Applicable

무연

Unknown

무할로겐

Unknown

분쟁 광물

Unknown

CerDIP-24 variants are typically not RoHS-compliant due to tin-lead ceramic packaging; check distributor material declarations. EP610 family predates AEC-Q100 qualification programs and is not automotive-qualified.

데이터 검증일: 2026-09-10 — XAIPART 부품 엔지니어링 팀이 검증하고 관리한 데이터

출처: Distributor, Manufacturer Datasheet, Manufacturer Datasheet, Manufacturer Datasheet, Distributor, Distributor