EP1810JC35 vs EP1810LC-25T 비교
다음의 상세 나란히 비교: EP1810JC35 제조: Altera 및 EP1810LC-25T 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1810JC35 | EP1810LC-25T |
|---|---|---|
| 브랜드 | Altera | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $8.40 |
| Family | Altera Classic EPLD | Altera Classic EP1810 |
| Product Type | UV-erasable / OTP Complex PLD (EPLD) | — |
| Macrocells | 48 | 48 (4 quadrants x 12 macrocells) |
| Logic Gates (typ.) | [DATA_NEEDED: logic gates count] | — |
| Maximum User I/O Pins | [DATA_NEEDED: user I/O count for PLCC-68] | — |
| Propagation Delay (tPD) | 35 ns | 25 ns |
| 최대 클록 주파수 | 40 MHz | — |
| Supply Voltage (VCC max) | 5.25 V | — |
| Supply Voltage (VCC min) | [DATA_NEEDED: VCC minimum] | — |
| Process Technology | CMOS EPROM cell | — |
| 동작 온도 | 0 C to +70 C (Commercial) | 0 °C to +70 °C (commercial) |
| 패키지 | PLCC-68 (J-lead, ceramic) | 28-pin J-lead PLCC (Plastic Leaded Chip Carrier) |
| Package Code | QCCJ | — |
| Terminal Form | J-BEND | — |
| Number of Terminals | 68 | — |
| Programming | UV-erase (windowed) or OTP | — |
| Development Tool | Altera MAX+plus II / A+plus | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance for EP1810JC35] | [DATA_NEEDED: RoHS status - confirm with manufacturer] |
| Device Type | — | EPLD (Erasable/OTP Complex PLD) |
| Usable Gates | — | Approx. 900 |
| Dedicated Inputs | — | 16 |
| Bidirectional I/O Pins | — | 48 |
| External Clocks | — | 4 |
| Supply Voltage (VCC) | — | 5 V nominal |
| 실장 유형 | — | Surface Mount |
| Technology | — | CMOS, UV-erasable / OTP |
| I/O Standard | — | TTL-compatible 5 V |
| Programming Tool | — | Altera MAX+PLUS II / Quartus Classic |