EP1SGX25FF1020C6N vs EP1SGX25FF1020 비교
다음의 상세 나란히 비교: EP1SGX25FF1020C6N 제조: Intel 및 EP1SGX25FF1020 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP1SGX25FF1020C6N | EP1SGX25FF1020 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $160.00 | $295.00 |
| Family | Stratix GX | Stratix GX |
| Series | Stratix | — |
| Logic Elements | 25 660 | — |
| Number of LABs/CLBs | 2566 | — |
| Number of User I/O | 607 | — |
| 패키지 | 1020-ball FC-FBGA, 33 x 33 mm, 1 mm pitch | 1020-ball FCBGA (PBGA, 1.00 mm pitch) |
| Supply Voltage (Core) | 1.5 V | — |
| Process Technology | CMOS | 130 nm CMOS |
| 동작 온도 | 0 °C to 85 °C (commercial) | -40C to +85C (industrial variant) / 0C to +85C (commercial variant) |
| Speed Grade | C6 | — |
| Lead-Free (Pb-Free) | Yes | — |
| RoHS 상태 | Compliant (per Altera/Intel product page) | [DATA_NEEDED: RoHS compliance status] |
| 실장 유형 | Surface Mount (BGA) | Surface Mount (BGA) |
| Transceivers | Multi-gigabit transceivers (3.125 Gbps class) - exact channel count [DATA_NEEDED] | — |
| Embedded Memory | RAM blocks (M512/M4K/M-RAM) - exact total bits [DATA_NEEDED] | — |
| Embedded Multipliers | DSP blocks present - exact count [DATA_NEEDED] | — |
| Global Clocks | Up to 20 (Stratix GX family) | — |
| Configuration | Serial / Parallel (Altera Stratix GX family) | — |
| Logic Elements (LE) | — | 25,660 |
| Configurable Logic Blocks (CLB) | — | 2,566 |
| Embedded Memory (bits) | — | 1,944,576 |
| Logic Cells (per FPGAkey) | — | 25,660 |
| Combinatorial Delay (Tpd) | — | 7.49 ns (per Microchip USA datasheet summary) |
| Operating Frequency (max) | — | [DATA_NEEDED: max internal operating frequency] |
| Pin/Package Count | — | 1020 |
| 공급 전압 | — | [DATA_NEEDED: core VCC voltage] |
| Serial Transceivers | — | Embedded SERDES (multi-gigabit, protocol-dependent) |
| DSP Blocks | — | Embedded dedicated multipliers |
| PLL / Clock Management | — | Embedded PLLs |
| Configuration Method | — | SRAM-based, configuration via JTAG / passive serial / fast passive parallel |