EP20K400GI655-3V vs EP20K400GI655-3 비교
다음의 상세 나란히 비교: EP20K400GI655-3V 제조: Intel 및 EP20K400GI655-3 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Intel
EP20K400GI655-3V - APEX 20K 400K-Gate FPGA, 16K LE, 655-Pin PGA | Altera (Intel)
EP20K400GI655-3V Obsolete사양 비교
| 파라미터 | EP20K400GI655-3V | EP20K400GI655-3 |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $142.50 | $55.00 |
| Series | APEX 20K | — |
| Device Family | EP20K400 | — |
| Logic Elements | 16,640 | — |
| Typical Gate Count | 400,000 gates | — |
| Maximum User I/O | 496 | 502 |
| Dedicated Inputs | 6 | 4 |
| Embedded System Blocks (ESBs) | [DATA_NEEDED: ESB count] | — |
| Total Embedded RAM | [DATA_NEEDED: total RAM bits] | — |
| Technology | CMOS (0.18 µm process) | — |
| Maximum Internal Clock Frequency | 714.2 MHz | — |
| Supply Voltage VCCINT | 2.5 V | — |
| I/O Supply Voltage VCCIO | 2.5 V or 3.3 V | — |
| 패키지 | 655-pin SPGA (Staggered PGA), 47 x 47 mm | 655-Pin PGA (Plastic/CPGA, square) |
| 실장 유형 | Through-Hole (Pin Grid Array) | Through-Hole (Socket) |
| 동작 온도 | -40 °C to +85 °C (industrial) | 0°C to 70°C (Industrial I grade) |
| 습도 민감도 레벨 (MSL) | 1 | — |
| Qualification | Not Qualified | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Configuration Interface | IEEE 1149.1 JTAG + serial / parallel passive | — |
| Family | — | APEX 20KE |
| Logic Elements / Cells | — | 16,640 |
| System Gates | — | 400,000 (maximum) |
| Number of Terminals | — | 655 |
| JESD-30 Code | — | S-CPGA-P655 |
| Package Shape | — | Square |
| Form of Terminal | — | PIN/PEG (through-hole) |
| Process Technology | — | CMOS, 2.5V core |
| Core Supply Voltage | — | 2.5 V |
| I/O Supply Voltage | — | 2.5 V or 3.3 V (MultiVolt I/O) |
| Speed Grade | — | -3 (slowest of the EP20K400 family) |
| Configuration Modes | — | Passive Serial, Passive Parallel Asynchronous, JTAG |
| Embedded Memory | — | Dual-port RAM via Embedded System Blocks (ESBs) |
| JTAG / Boundary Scan | — | IEEE 1149.1 compliant |