EP3SE50F484C2G vs EP3SL50F484C2N 비교
다음의 상세 나란히 비교: EP3SE50F484C2G 제조: Intel 및 EP3SL50F484C2N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP3SE50F484C2G | EP3SL50F484C2N |
|---|---|---|
| 브랜드 | Intel | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | 최종 구매 | 최종 구매 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $1,180.00 | $175.00 |
| Series | Stratix III E | Stratix III L |
| Number of Logic Elements / Cells | 47,500 | — |
| Number of LABs / CLBs | 1,900 | — |
| Total RAM Bits | 5,760,000 (5,760 Kbit) | — |
| Number of User I/O | 296 | — |
| 패키지 / 케이스 | 484-BBGA, FCBGA (FineLine BGA) | — |
| 실장 유형 | Surface Mount | Surface Mount |
| Core Voltage Supply | 0.86 V to 1.15 V | — |
| 동작 온도 | 0 °C to +85 °C (TJ) | — |
| Process Technology | 40 nm TSMC low-power CMOS | 65 nm |
| Logic Element Architecture | Adaptive Logic Module (ALM) with 8-input fracturable LUT | — |
| Embedded DSP Blocks | Yes (variable-precision multipliers) | — |
| Transceivers | Multi-gigabit transceivers (selected package pins) | — |
| Memory Interface Support | DDR / DDR2 / DDR3 with hard PHY | — |
| Partial Reconfiguration | Supported | — |
| Configuration Interface | JTAG, Passive Serial, Fast Passive Parallel | — |
| Part Status | Active (Intel catalogue); long-term supply subject to Stratix III lifecycle policy | — |
| RoHS 상태 | Compliant | — |
| Family | — | Stratix III |
| Logic Elements | — | 47,500 |
| Logic Array Blocks (LABs) | — | 1,900 |
| Embedded Memory | — | 2,184,192 bits |
| User I/Os | — | 296 |
| Operating Frequency | — | 600 MHz |
| Core Supply Voltage | — | 1.1 V |
| 패키지 | — | 484-ball FC-FBGA (Flip-Chip) |
| Package Code | — | BGA |
| Package Shape | — | Square |
| Temperature Grade | — | Industrial (C2) |
| Lead-Free / RoHS | — | Yes (compliant) |
| MSL 레벨 | — | [DATA_NEEDED: MSL level] |
| Configuration Method | — | JTAG / Passive Serial / FPP |