EP910DC-35 vs EP910DI-35 비교

다음의 상세 나란히 비교: EP910DC-35 제조: Altera 및 EP910DI-35 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EP910DC-35 EP910DI-35
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete 활성
재고 상태 In Stock In Stock
단가 (USD) $10.95 $35.20
Device Type UV-Erasable CMOS PLD (PAL-type) —
Family Classic EPLD EP910 Altera Classic EPLD
Architecture PAL-type sum-of-products AND-OR array —
Usable Gates 900 gates 450
Macrocells 24 24
Product Terms 240 —
Dedicated Inputs 12 10
I/O Pins 24 —
Total Inputs 36 —
Propagation Delay (tpd) 35 ns —
최대 클록 주파수 37 MHz (typical, internal) —
Supply Voltage (Vcc) 4.75 V to 5.25 V (5 V nominal) —
동작 온도 0 °C to +70 °C (commercial) -40C to +85C (industrial)
패키지 40-pin CDIP (Ceramic DIP) with quartz window CDIP-40 (Ceramic DIP with UV window)
Lead Pitch 2.540 mm —
Termination Style Through-Hole —
Programming Method JEDEC fuse map via device programmer; UV erase EPROM programmer + JEDEC fuse map
Technology CMOS, UV-erasable EPROM cell CMOS, UV-erasable EPROM
RoHS 상태 Non-compliant (ceramic DIP with Pb-bearing lead finish) [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Lifecycle Obsolete / last-time-buy from authorized distributors —
Product Type — EPLD (Erasable Programmable Logic Device)
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) — 40 mA typical
Bidirectional I/O Pins — 20
Total Pins — 40
실장 유형 — Through-Hole
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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