EPM3064ATC100-10 vs EPM3064AT100-10N 비교
다음의 상세 나란히 비교: EPM3064ATC100-10 제조: Altera 및 EPM3064AT100-10N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Altera
EPM3064ATC100-10 - 64-Macrocell MAX 3000A CPLD, 100MHz, TQFP-100 | Altera
EPM3064ATC100-10 Nrnd사양 비교
| 파라미터 | EPM3064ATC100-10 | EPM3064AT100-10N |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | NRND | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $2.85 | $5.45 |
| Family | MAX 3000A | MAX 3000A |
| Logic Gates | 1250 gates | — |
| Macrocells | 64 | 64 |
| Logic Array Blocks | 2 | — |
| User I/O Pins | 34 | 66 |
| 패키지 | TQFP-100 (100-pin Thin Quad Flat Pack) | TQFP-100 (T100), 14 mm x 14 mm |
| Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.3 V |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | IEEE Std. 1149.1 (JTAG) and IEEE Std. 1532 compliant | — |
| Global Clock Signals | 2 (with optional inversion) | — |
| Output Enable Signals | 6 or 10 pin- or logic-driven | — |
| Output Slew-Rate Control | Programmable | — |
| Operating Temperature Grade | Commercial | — |
| MultiVolt I/O Support | 1.5V / 1.8V / 2.5V / 3.3V interfaces | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 4 |
| Usable Gates | — | 1,250 |
| Speed Grade | — | -10 (10 ns pin-to-pin delay) |
| I/O Bank Voltage | — | 3.3 V |
| 5 V Tolerant Inputs | — | Yes (via clamping diodes) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std. 1149.1) with pin-locking |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary-Scan Test (BST) | — | IEEE Std. 1149.1 compliant |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Lead-Free | — | [DATA_NEEDED: lead-free finish] |