EPM5064JC vs EPM5032JC25 비교
다음의 상세 나란히 비교: EPM5064JC 제조: Altera 및 EPM5032JC25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5064JC | EPM5032JC25 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $7.10 | $23.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | — |
| Macrocells | 64 | — |
| Usable Gates | 1,250 (approx.) | — |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| 패키지 | 68-pin PLCC (JEDEC) | 28-pin PLCC (JC) |
| 실장 유형 | Surface Mount (socketed) | Surface Mount |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | — |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| 동작 온도 | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 레벨 | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Device | — | EPM5032 |
| Logic Elements | — | 32 macrocells |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Internal Frequency | — | 62.5 MHz |
| Product Terms | — | 320 |
| Flip-Flops | — | 32 |
| Dedicated Inputs | — | 7 |
| Bidirectional I/O Pins | — | 16 |
| Total Inputs to Array | — | 24 |
| 출력 수 | — | 16 |
| Architecture | — | PAL-type macrocells with global Programmable Interconnect Array (PIA) |
| Technology | — | CMOS EPROM, UV-erasable (windowed) / OTP |
| 공급 전압 | — | 5 V (TTL-level I/O) |