EPM5064JC vs EPM5032JC25 Comparison

Detailed side-by-side comparison of EPM5064JC by Altera and EPM5032JC25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5064JC EPM5032JC25
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $7.10 $23.95
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable PLD) β€”
Macrocells 64 β€”
Usable Gates 1,250 (approx.) β€”
Logic Array Inputs 36 β€”
Logic Array Outputs 64 β€”
Package 68-pin PLCC (JEDEC) 28-pin PLCC (JC)
Mounting Type Surface Mount (socketed) Surface Mount
Supply Voltage (VCC) 5 V (typical, 4.75 V - 5.25 V range) β€”
I/O Logic Level TTL / CMOS compatible β€”
Configuration Memory EPROM (UV-erasable window or OTP) β€”
Operating Temperature [DATA_NEEDED: operating temperature grade] β€”
Pin-to-Pin Delay (tPD) [DATA_NEEDED: specific tPD grade value] β€”
Maximum Frequency (fMAX) [DATA_NEEDED: fCNT grade value] β€”
RoHS Status [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] β€”
MSL Level [DATA_NEEDED: MSL rating] β€”
Programming Tool Altera MAX+PLUS II / Quartus II (legacy device support) β€”
Device β€” EPM5032
Logic Elements β€” 32 macrocells
Propagation Delay (tPD) β€” 25 ns
Maximum Internal Frequency β€” 62.5 MHz
Product Terms β€” 320
Flip-Flops β€” 32
Dedicated Inputs β€” 7
Bidirectional I/O Pins β€” 16
Total Inputs to Array β€” 24
Number of Outputs β€” 16
Architecture β€” PAL-type macrocells with global Programmable Interconnect Array (PIA)
Technology β€” CMOS EPROM, UV-erasable (windowed) / OTP
Supply Voltage β€” 5 V (TTL-level I/O)

Datasheets & Resources

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