EPM5128GC-1 vs EPM5064JC 비교
다음의 상세 나란히 비교: EPM5128GC-1 제조: Altera 및 EPM5064JC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5128GC-1 | EPM5064JC |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $18.95 | $7.10 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-erasable CMOS CPLD | EPLD (Erasable PLD) |
| Macrocells | 128 | 64 |
| Usable Gates | 2,500 | 1,250 (approx.) |
| Dedicated Inputs | 7 | — |
| Maximum User I/O Pins | 52 | — |
| Nominal Supply Voltage | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 16 ns (typical, -1 speed grade) | — |
| 패키지 | PGA-96+ (Pin Grid Array, ceramic windowed) | 68-pin PLCC (JEDEC) |
| Technology | CMOS, UV-erasable EPROM | — |
| 동작 온도 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature grade] |
| IOL / IOH | 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) | — |
| Security Bit | Programmable, prevents readback | — |
| Programming Method | UV erase + EPROM program (or device programmer) | — |
| MSL 레벨 | [DATA_NEEDED: MSL level] | [DATA_NEEDED: MSL rating] |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] | [DATA_NEEDED: RoHS compliance] |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 실장 유형 | — | Surface Mount (socketed) |
| Supply Voltage (VCC) | — | 5 V (typical, 4.75 V - 5.25 V range) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |