EPM5128GC-1 vs EPM5064JC Comparação

Comparação detalhada lado a lado de EPM5128GC-1 por Altera e EPM5064JC por Altera. Compare especificações principais, parâmetros elétricos, encapsulamento, status do ciclo de vida, preços e disponibilidade para determinar o melhor componente para os requisitos do seu projeto.

Comparação de especificações

Parâmetro EPM5128GC-1 EPM5064JC
Marca Altera Altera
Categoria FPGA & CPLD FPGA & CPLD
Status do ciclo de vida Obsolete Obsolete
Status do estoque In Stock In Stock
Preço unitário (USD) $18,95 $7,10
Family MAX 5000 MAX 5000
Device Type UV-erasable CMOS CPLD EPLD (Erasable PLD)
Macrocells 128 64
Usable Gates 2,500 1,250 (approx.)
Dedicated Inputs 7 —
Maximum User I/O Pins 52 —
Nominal Supply Voltage 5 V —
Supply Voltage Range 4.75 V to 5.25 V —
Maximum Operating Frequency 62.5 MHz —
Propagation Delay (tPD) 16 ns (typical, -1 speed grade) —
Encapsulamento PGA-96+ (Pin Grid Array, ceramic windowed) 68-pin PLCC (JEDEC)
Technology CMOS, UV-erasable EPROM —
Temperatura de operação -40C to +85C (industrial) [DATA_NEEDED: operating temperature grade]
IOL / IOH 100 mA / 25 mA per pin (legacy figure, [DATA_NEEDED: verify exact drive spec]) —
Security Bit Programmable, prevents readback —
Programming Method UV erase + EPROM program (or device programmer) —
Nível MSL [DATA_NEEDED: MSL level] [DATA_NEEDED: MSL rating]
Status RoHS [DATA_NEEDED: RoHS compliance - ceramic PGA part is legacy] [DATA_NEEDED: RoHS compliance]
Logic Array Inputs — 36
Logic Array Outputs — 64
Tipo de montagem — Surface Mount (socketed)
Supply Voltage (VCC) — 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

Fichas técnicas e recursos

Ver todos os produtos Criar BOM Solicitar cotação