EPM5128JC vs EPM5064JC 비교
다음의 상세 나란히 비교: EPM5128JC 제조: Altera 및 EPM5064JC 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5128JC | EPM5064JC |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $7.10 |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | EPLD (Erasable PLD) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | 5 V (typical, 4.75 V - 5.25 V range) |
| 핀 수 | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | — |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | — |
| Configuration Memory | UV-erasable EPROM (windowed package) | EPROM (UV-erasable window or OTP) |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| 동작 온도 | Commercial 0C to +70C | [DATA_NEEDED: operating temperature grade] |
| 실장 유형 | Surface Mount (PLCC socket or solder) | Surface Mount (socketed) |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| RoHS 상태 | [DATA_NEEDED: RoHS status - legacy part] | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | [DATA_NEEDED: lead-free status] | [DATA_NEEDED: lead-free status] |
| Family | — | MAX 5000 |
| Macrocells | — | 64 |
| Usable Gates | — | 1,250 (approx.) |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 패키지 | — | 68-pin PLCC (JEDEC) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| MSL 레벨 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |