EPM5192AGC84-20 vs EPM5192AGC-15 비교
다음의 상세 나란히 비교: EPM5192AGC84-20 제조: Altera 및 EPM5192AGC-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192AGC84-20 | EPM5192AGC-15 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $41.20 | $27.80 |
| Product Type | Complex Programmable Logic Device (CPLD) | EPLD (Erasable Programmable Logic Device) |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| 패키지 | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | Ceramic Pin Grid Array (PGA) |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | — |
| Operating Temperature Grade | Commercial | — |
| 공급 전압 | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] |
| 실장 유형 | Through-Hole (Pin Grid Array socket) | — |
| Series | — | MAX 5000 |
| Logic Array Blocks | — | 16 (typical for 192-macrocell MAX 5000) |
| Maximum User I/O Pins | — | 64 |
| Total Inputs | — | 72 |
| Propagation Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Supply Voltage (VCC) | — | 5 V |
| Technology | — | CMOS, UV-erasable EPROM |
| Programming Method | — | UV erase + EPROM program (via Altera programmer) |
| 동작 온도 | — | [DATA_NEEDED: operating temperature range] |
| 수명 주기 상태 | — | Obsolete / Last Time Buy (per Altera legacy product list) |