EPM5192AGC84-20 vs EPM5192AJI84-15 비교
다음의 상세 나란히 비교: EPM5192AGC84-20 제조: Altera 및 EPM5192AJI84-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192AGC84-20 | EPM5192AJI84-15 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $41.20 | $27.80 |
| Product Type | Complex Programmable Logic Device (CPLD) | UV-Erasable / OTP Complex PLD |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| 패키지 | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS EPROM (UV-erasable) |
| Operating Temperature Grade | Commercial | — |
| 공급 전압 | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance] | unknown |
| 실장 유형 | Through-Hole (Pin Grid Array socket) | Through-Hole (SMD socket-compatible) |
| Device Family | — | MAX 5000 EPLD |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Package Type | — | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window |
| 동작 온도 | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Programming Method | — | UV erase + EPROM program via standard Altera programmer |
| Design Tool Support | — | MAX+PLUS II (legacy); not supported by modern Quartus Prime |
| Lead-Free | — | unknown |
| 할로겐 프리 | — | unknown |
| Functional Equivalent (Plastic OTP) | — | EPM5192AJC84-15 (windowless plastic JLCC, same die) |