EPM5192AGC84-20 vs EPM5192AJI84-15 对比
详细并排对比 EPM5192AGC84-20 出自 Altera 和 EPM5192AJI84-15 出自 Altera。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况，以确定最适合您设计需求的元器件。
规格对比
| 参数 | EPM5192AGC84-20 | EPM5192AJI84-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 分类 | FPGA & CPLD | FPGA & CPLD |
| 生命周期状态 | Obsolete | Obsolete |
| 库存状态 | 有库存 | 有库存 |
| 单价（USD） | $41.20 | $27.80 |
| Product Type | Complex Programmable Logic Device (CPLD) | UV-Erasable / OTP Complex PLD |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 84 |
| Dedicated Inputs | 7 | — |
| Logic Gates (typical) | [DATA_NEEDED: typical gate count] | — |
| Maximum Clock Frequency (fMAX) | 66.7 MHz | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Speed Grade | -20 | — |
| 封装 | 84-pin Ceramic Pin Grid Array (CPGA, WPGA) | — |
| Package Code | WPGA | — |
| Erasure Method | UV-Erasable (with OTP window) | — |
| Process Technology | CMOS | CMOS EPROM (UV-erasable) |
| Operating Temperature Grade | Commercial | — |
| 电源电压 | [DATA_NEEDED: VCC range] | — |
| I/O Standard | 5V CMOS / TTL compatible | — |
| RoHS 状态 | [DATA_NEEDED: RoHS compliance] | unknown |
| 安装类型 | Through-Hole (Pin Grid Array socket) | Through-Hole (SMD socket-compatible) |
| Device Family | — | MAX 5000 EPLD |
| Logic Array Blocks (LABs) | — | 16 |
| Propagation Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.5 V to 5.5 V (nominal 5 V) |
| Package Type | — | 84-pin JLCC (J-Leaded Ceramic Chip Carrier) with quartz window |
| 工作温度 | — | -40 °C to +85 °C (Industrial, 'I' suffix) |
| Programming Method | — | UV erase + EPROM program via standard Altera programmer |
| Design Tool Support | — | MAX+PLUS II (legacy); not supported by modern Quartus Prime |
| Lead-Free | — | unknown |
| 无卤 | — | unknown |
| Functional Equivalent (Plastic OTP) | — | EPM5192AJC84-15 (windowless plastic JLCC, same die) |