EPM5192JC vs EPM5192JC-ES 비교
다음의 상세 나란히 비교: EPM5192JC 제조: Intel 및 EPM5192JC-ES 제조: Intel. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192JC | EPM5192JC-ES |
|---|---|---|
| 브랜드 | Intel | Intel |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $16.40 | $16.45 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 패키지 | 68-pin PLCC (JC) windowed ceramic | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| 실장 유형 | Surface Mount | Surface Mount |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 동작 온도 | [DATA_NEEDED: commercial / industrial / military grade] | [DATA_NEEDED: operating temperature range for ES grade] |
| 공급 전압 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS 상태 | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Device Type | — | CPLD (EPLD) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| User I/O Pins | — | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 레벨 | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |