EPM5192LC-2N vs EPM5192LC-25 비교
다음의 상세 나란히 비교: EPM5192LC-2N 제조: Altera 및 EPM5192LC-25 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPM5192LC-2N | EPM5192LC-25 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $11.85 | $55.00 |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Flip-Flops | 192 | — |
| Logic Elements | 192 macrocells (PAL/GAL-style AND-OR array) | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Package Type | LC (ceramic J-leaded, windowed UV-erasable package family) | — |
| Speed Grade | -2 (tPD approximately 25 ns) | -25 (25 ns) |
| Propagation Delay (typical) | 25 ns | — |
| 공급 전압 | 5 V (typical) | 5 V (typical, MAX 5000) |
| Programmability | UV-erasable EPROM cell | — |
| 실장 유형 | Surface Mount (LC package) | Surface Mount |
| 동작 온도 | Commercial (0C to +70C) - inferred from speed-grade -2 designation | 0C to +70C (commercial) |
| RoHS 상태 | Compliant (per -N lead-free suffix) | Unknown (legacy ceramic package typically non-RoHS) |
| Lead-Free | Yes (per -N suffix) | — |
| Architecture | Programmable Logic Array (PLA) with global PIA | — |
| Programming Interface | Altera programming hardware (MAX+PLUS II / ByteBlaster compatible) | JTAG / Altera programming hardware (legacy) |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| 패키지 | — | JLCC-84 (ceramic J-lead chip carrier) |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| I/O Standard | — | TTL-compatible |
| Configuration Memory | — | Non-volatile EPROM (on-chip) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |