EPM570GT100I5 vs EPM570F100I5N 비교

다음의 상세 나란히 비교: EPM570GT100I5 제조: Altera 및 EPM570F100I5N 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM570GT100I5 EPM570F100I5N
브랜드 Altera Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 활성 활성
재고 상태 In Stock In Stock
단가 (USD) $4.95 $13.40
Series MAX II —
Logic Elements (LE) 570 —
Macrocells 440 440
Maximum User I/O Pins 76 —
Propagation Delay (tPD) 5.4 ns (typ) 8.7 ns (max), 5.4 ns (typical)
Internal Supply Voltage (VCCINT) 1.71 V to 1.89 V —
User I/O Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
User Flash Memory 8 Kbits 8 Kbits
Programmability In-System Programmable (ISP) via JTAG, non-volatile flash —
Configuration Time Instant-On (< 1 ms, no external PROM required) —
동작 온도 -40 C to +100 C (Industrial, "I5") -40C to +100C (Industrial)
패키지 100-pin TQFP (14x14 mm, 0.5 mm pitch) 100-ball FineLine BGA (11x11 mm)
실장 유형 Surface Mount (Gull-wing leads) Surface Mount
Typical Active Current [DATA_NEEDED: typical active ICC] —
Speed Grade GT (fast) —
RoHS 상태 Compliant Compliant
JTAG Support IEEE 1149.1 boundary scan —
Global Clock Networks 4 —
Family — MAX II
Device Type — CPLD (Flash-based)
Logic Elements (LEs) — 570
Maximum User I/Os — 76
Maximum Operating Frequency — 304 MHz
Supply Voltage (VCCINT) — 2.375 V to 3.6 V
Typical Supply Current (ICC) — 55 mA
I/O Standards Supported — LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V)
Programming Interface — JTAG (IEEE 1149.1), in-system programmable
Global Clocks — 4
Process Technology — CMOS, Flash configuration cell
Hot Socketing — Supported

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