EPM7160SLC84-6 vs EPM7160SLC84-15 비교

다음의 상세 나란히 비교: EPM7160SLC84-6 제조: Intel 및 EPM7160SLC84-15 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.

사양 비교

파라미터 EPM7160SLC84-6 EPM7160SLC84-15
브랜드 Intel Altera
카테고리 FPGA & CPLD FPGA & CPLD
수명 주기 상태 Obsolete Obsolete
재고 상태 In Stock In Stock
단가 (USD) $15.86 $10.80
Family MAX 7000S MAX 7000
Device Type EE PLD (CPLD) —
Macrocells 160 160
Logic Array Blocks (LABs) 4 (16 macrocells each) —
Usable Gates 3.2K 3,200
User I/O Pins 36 (also reported as 64 depending on source) —
Pin-to-Pin Delay (tPD) 6 ns (speed grade -6) —
Counter Frequency (fCNT) 149.3 MHz —
공급 전압 4.75 V to 5.25 V (single 5 V supply) —
Process Technology CMOS EEPROM —
In-System Programmability Yes (5.0 V ISP via JTAG) —
JTAG Support IEEE Std. 1149.1 compliant —
MultiVolt I/O Yes (mixed-voltage interface) —
패키지 84-pin PLCC (29.31 x 29.31 mm) —
실장 유형 Surface Mount (J-Lead) Surface Mount (PLCC socket or direct solder)
동작 온도 [DATA_NEEDED: commercial vs industrial grade] 0 C to 70 C
RoHS 상태 Compliant Not RoHS compliant (contains lead, SnPb finish typical)
Maximum Propagation Delay — 15 ns
Maximum User I/O Pins — 64
Supply Voltage (VCCINT/VCIO) — 4.75 V to 5.25 V (5 V nominal)
I/O Logic Level — Configurable 3.3 V or 5 V
Technology — CMOS, EEPROM configuration
Package Type — PLCC-84 (PQCC84, JEDEC S-PQCC-J84)
Terminal Pitch — 1.270 mm
Programming Interface — JTAG (IEEE 1149.1) in-system programmable
Lifecycle — Obsolete / last-time-buy (per Altera/Intel PDN)

데이터시트 & 자료

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