LTC2261IUJ-14 vs LTC2257IUJ-14 비교
다음의 상세 나란히 비교: LTC2261IUJ-14 제조: Analog Devices 및 LTC2257IUJ-14 제조: Analog Devices. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
Analog Devices
LTC2257IUJ-14 - 14-bit, 40Msps Ultralow Power 1.8V ADC | Analog Devices
LTC2257IUJ-14 ✓ 활성사양 비교
| 파라미터 | LTC2261IUJ-14 | LTC2257IUJ-14 |
|---|---|---|
| 브랜드 | Analog Devices | Analog Devices |
| 카테고리 | ADC/DAC | ADC/DAC |
| 수명 주기 상태 | 활성 | 활성 |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $26.80 | $16.40 |
| 분해능 | 14 bits | 14 bit |
| Sample Rate | 125 Msps | 40 Msps |
| Architecture | Pipelined | Pipelined |
| Number of Channels | 1 | — |
| Input Type | Differential (single-ended capable with biasing) | Differential (single-ended capable) |
| Analog Supply Voltage (AVDD) | 1.8 V | — |
| Output Supply Voltage (OVDD) | 1.2 V to 1.8 V | — |
| Integral Nonlinearity (INL) | ±1 LSB (typical) | — |
| Differential Nonlinearity (DNL) | ±0.3 LSB (typical) | — |
| Transition Noise | 1.2 LSB RMS | 1.13 LSB RMS |
| Signal-to-Noise Ratio (SNR) | 73.4 dB | — |
| Spurious-Free Dynamic Range (SFDR) | 85 dB | — |
| Missing Codes | None over temperature | None over temperature |
| Digital Output Modes | Full-rate CMOS, DDR CMOS, DDR LVDS | — |
| 동작 온도 범위 | -40 °C to +85 °C (I grade) | — |
| 패키지 | 40-pin QFN (6x6 mm) with exposed pad | 40-QFN (UJ) 6x6 mm with exposed pad |
| 실장 유형 | Surface Mount | Surface Mount |
| RoHS 상태 | Compliant (PBF suffix) | Compliant (#PBF suffix) |
| Number of Inputs | — | 1 |
| Analog Supply Voltage | — | 1.7 V to 1.9 V (1.8 V nominal) |
| Digital Output Supply | — | 1.2 V to 1.8 V |
| Power Dissipation | — | [DATA_NEEDED: exact mW at 40 Msps, datasheet figure] |
| INL (typical) | — | ±1 LSB |
| DNL (typical) | — | ±0.3 LSB |
| Output Interface | — | CMOS / DDR CMOS / DDR LVDS (selectable) |
| SNR | — | [DATA_NEEDED: SNR dBFS at fin] |
| SFDR | — | [DATA_NEEDED: SFDR dBc at fin] |
| 동작 온도 | — | -40C to +85C (I grade) |
| Configuration Interface | — | SPI serial port |
| Power-Saving Modes | — | Shutdown, Nap modes |
| Clock Duty-Cycle Stabilizer | — | Optional, on-chip |
| Reference Type | — | External or internal (per variant) |